Datasheet

13
LTC1594L/LTC1598L
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APPLICATIONS INFORMATION
WUU
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Operation with D
IN
and D
OUT
Tied Together
The LTC1594L/LTC1598L can be operated with D
IN
and
D
OUT
tied together. This eliminates one of the lines
required to communicate to the microprocessor (MPU).
Data is transmitted in both directions on a single wire.
The processor pin connected to this data line should be
configurable as either an input or an output. The
LTC1594L/LTC1598L will take control of the data line
after CS falling and before the 6th falling CLK while the
processor takes control of the data line when CS is high
(see Figure 3). Therefore the processor port line must be
switched to an input with CS being low to avoid a conflict.
Separate Chip Selects for MUX and ADC
The LTC1594L/LTC1598L provide separate chip selects,
CSMUX and CSADC, to control MUX and ADC separately.
This feature not only provides the flexibility to select a
particular channel once for multiple conversions (see
Figure 4) but also maximizes the sample rate up to
20ksps (see Figure 5).
Figure 4. Selecting a Channel Once for Multiple Conversions
CLK
EN D1
D2
CSADC
CSMUX
B5
B6
B7
B8B9
B10B11
Hi-Z
D
OUT
CH0 TO
CH7
D
IN
t
CONV
Hi-Z
t
suCS
NULL
BIT
D0
B4
B3
B2 B1 B0
t
SMPL
t
ON
B5
B6
B7
B8B9
B10B11
Hi-Z
t
CONV
t
suCS
NULL
BIT
D0
B4
B3
B2 B1 B0
t
SMPL
ADCIN =
MUXOUT
COM = GND
1594L/98L F04
DON’T CARE
DON’T CARE
1
2 3 456
CS
CLK
DATA (D
IN
/D
OUT
)
EN D2 D1 D0 B11 B10
•••
LTC1594L/LTC1598L CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO MPU
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1594L/LTC1598L
PROCESSOR MUST RELEASE DATA
LINE AFTER CS FALLING AND
BEFORE THE 6TH FALLING CLK
LTC1594L/LTC1598L TAKES CONTROL OF DATA
LINE AFTER CS FALLING AND BEFORE THE
6TH FALLING CLK
1594L/98L F03
t
suCS
Figure 3. LTC1594L/LTC1598L Operation with D
IN
and D
OUT
Tied Together