Datasheet

3
LTC1569-7
Output DC Offset R
EXT
= 10k, Pin 5 Shorted to Pin 4 V
S
= 3V ±2 ±5mV
(Note 2) V
S
= 5V ±6 ±12 mV
V
S
= ±5V ±15 mV
Output DC Offset Drift R
EXT
= 10k, Pin 5 Shorted to Pin 4 V
S
= 3V –25 µV/°C
V
S
= 5V –25 µV/°C
V
S
= ±5V ±25 µV/°C
Clock Pin Logic Thresholds V
S
= 3V Min Logical “1” 2.6 V
when Clocked Externally Max Logical “0” 0.5 V
V
S
= 5V Min Logical “1” 4.0 V
Max Logical “0” 0.5 V
V
S
= ±5V Min Logical “1” 4.0 V
Max Logical “0” 0.5 V
Power Supply Current f
CLK
= 1.028MHz (10k from Pin 6 to Pin 7, V
S
= 3V 6 8 mA
(Note 3) Pin 5 Open, ÷ 4), f
CUTOFF
= 32kHz ● 9mA
V
S
= 5V 7 9 mA
● 10 mA
V
S
= 10V 9 13 mA
● 14 mA
f
CLK
= 4.096MHz (10k from Pin 6 to Pin 7, V
S
= 3V 9.5 mA
Pin 5 Shorted to Pin 4, ÷ 1), f
CUTOFF
= 128kHz ● 14 mA
f
CLK
= 8.192MHz (5k from Pin 6 to Pin 7, V
S
= 5V 20 mA
Pin 5 Shorted to Pin 4, ÷ 1), f
CUTOFF
= 256kHz ● 30 mA
V
S
= 10V 27 mA
● 37 mA
Power Supply Voltage where Pin 5 Shorted to Pin 4, Note 3 ● 3.7 4.2 4.6 V
Low Power Mode is Enabled
Clock Feedthrough R
EXT
= 10k, Pin 5 Open 0.4 mV
RMS
Wideband Noise Noise BW = DC to 2 • f
CUTOFF
125 µV
RMS
THD f
IN
= 10kHz, 1.5V
P-P
74 dB
Clock-to-Cutoff 32
Frequency Ratio
Max Clock Frequency V
S
= 3V 5 MHz
(Note 4) V
S
= 5V 9.6 MHz
V
S
= ±5V 13 MHz
Min Clock Frequency 3V to ±5V, T
A
< 85°C3kHz
(Note 5)
Input Frequency Range Aliased Components <–65dB 0.9 • f
CLK
Hz
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T
A
= 25°C.
V
S
= 3V (V
+
= 3V, V
–
= 0V), f
CLK
= 4.096MHz, f
CUTOFF
= 128kHz, R
LOAD
= 10k unless otherwise specified.
E
LECTR
IC
AL C CHARA TERIST
ICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: DC offset is measured with respect to Pin 3.
Note 3: There are several operating modes which reduce the supply
current. For V
S
< 4V, relative to divide-by-1 mode, the current is typically
reduced by 50% relative to V
S
= 5V. If the internal oscillator is used as the
clock source and the divide-by-4 or divide-by-16 mode is enabled, the
supply current is typically reduced by 60%,relative to divide-by-1 mode,
independent of the value of V
S
.
Note 4: The maximum clock frequency is arbitrarily defined as the
frequency at which the filter AC response exhibits >1dB of gain peaking.
Note 5: The minimum clock frequency is arbitrarily defined as the frequecy
at which the filter DC offset changes by more than 5mV.
Note 6: Thermal resistance varies depending upon the amount of PC board
metal attached to the device. θ
JA
is specified for a 2500mm
2
test board
covered with 2oz copper on both sides.