Datasheet

LTC1555L-1.8
7
APPLICATIO S I FOR ATIO
WUU
U
This configuration is only allowed if the controller data
output pin is open drain (all SIM I/O pins are open drain).
Internal pull-up resistors are provided for both the DATA
pin and the I/O pin on the SIM side. The second method
is to use the DDRV pin to send data to the SIM and use the
DATA pin to receive data from the SIM. When the DDRV
pin is not used, it should either be left floating or tied to
DV
CC
.
Shutting Down the DV
CC
Supply
To conserve power, the DV
CC
supply may be shut down
while the V
IN
supply is still active. When the DV
CC
supply
is forced below 1.2V, an undervoltage lockout circuit
forces the LTC1555L-1.8 into shutdown mode regardless
of the status of the M0-M2 pins.
10kV ESD Protection
All pins that connect to the SIM (CLK, RST, I/O, V
CC
, GND)
withstand over 10kV of human body model ESD. In order
to ensure proper ESD protection, careful board layout is
required. The GND pin should be tied directly to a GND
plane. The V
CC
capacitor should be located very close to
the V
CC
pin and tied immediately to the GND plane.
CIN
RIN
DATA
DDRV
DV
CC
CLK
RST
I/O
V
CC
CLK TO SIM
RST TO SIM
DATA TO/FROM SIM
LTC1555L-1.8
CONTROLLER
SIDE
SIM SIDE
1555L F01a
Figure 1a. Level Translator Connections for
Bidirectional Controller DATA Pin
CIN
RIN
DATA
DDRV
DV
CC
CLK
RST
I/O
V
CC
CLK TO SIM
RST TO SIM
DATA FROM SIM
DATA TO SIM
LTC1555L-1.8
CONTROLLER
SIDE
SIM SIDE
1555L F01b
Figure 1b. Level Translator Connections for
One-Directional Controller Side DATA Flow