Datasheet
6
LTC1516
APPLICATIONS INFORMATION
WUU
U
Ultralow Quiescent Current (I
Q
< 5µA) Regulated
Supply
The LTC1516 contains an internal resistor divider (refer to
Block Diagram) which draws only 1.5µA (typ) from V
OUT
.
During no-load conditions, the internal load causes a
droop rate of only 150mV per second on V
OUT
with
C
OUT
= 10µF. Applying a 5Hz to 100Hz, 95% to 98% duty
cycle signal to the SHDN pin ensures that the circuit of
Figure 3 comes out of shutdown frequently enough to
maintain regulation during no-load or low-load condi-
tions. Since the part spends nearly all of its time in
shutdown, the no-load quiescent current (see Figure 4a) is
approximately equal to (V
OUT
)(1.5µA)/(V
IN
)(Efficiency).
The LTC1516 must be out of shutdown for a minimum
duration of 200µs to allow enough time to sense the output
and keep it in regulation. As the V
OUT
load current
increases, the frequency with which the part is taken out
of shutdown must also be increased to prevent V
OUT
from drooping below 4.8V during the OFF phase (see
Figure 4b). A 100Hz 98% duty cycle signal on the SHDN
pin ensures proper regulation with load currents as high
as 100µA. When load current greater than 100µA is
needed, the SHDN pin must be forced low as in normal
operation. The typical no-load supply current for this
circuit with V
IN
= 3V is only 3.2µA.
1
2
3
4
8
7
6
5
C1
–
SHDN
GND
C2
–
C1
+
V
IN
V
OUT
C2
+
LTC1516
0.22µF
FROM MPU
10µF
10µF
V
OUT
= 5V ±4%
SHDN PIN WAVEFORMS:
LOW I
Q
MODE (5Hz TO 100Hz, 95% TO 98% DUTY CYCLE)
I
OUT
≤ 100µA
V
OUT
LOAD ENABLE MODE
(I
OUT
= 100µA TO 50mA)
0.22µF
V
IN
= 2V TO 5V
+
+
1516 • F03
Figure 3. Ultralow Quiescent Current (<5µA) Regulated Supply
Figure 4b. Maximum SHDN OFF Time vs Output Load Current for
Ultralow I
Q
Operation
Figure 4a. No Load I
CC
vs Input Voltage for Circuit in Figure 3
OUTPUT CURRENT (µA)
1
10
100
1000
MAXIMUM SHDN OFF TIME (ms)
1000
1516 • F04b
1 10 100
SHDN ON PULSE WIDTH = 200µs
C
OUT
= 10µF
INPUT VOLTAGE (V)
0.0
2.0
4.0
6.0
SUPPLY CURRENT (µA)
5.0
1516 • F04a
2.0 3.0 4.0