Datasheet

4
LTC1516
BLOCK DIAGRAM
W
COMP1
COMP2
COMP3
V
REF
CLOCK 1
CLOCK 2
CONTROL
LOGIC
V
OS
S3
S2A
S2B
S2C
S1A
S1B
S1C
S1D
0.22µF
10µF
0.22µF
C1
+
C1
–
C2
+
C2
–
10µF
V
OUT
SHDN
LTC1516 • BD
CHARGE PUMP SHOWN IN TRIPLER MODE, DISCHARGE CYCLE
V
IN
CHARGE PUMP
+
+
APPLICATIONS INFORMATION
WUU
U
Operation
The LTC1516 uses a switched capacitor charge pump to
boost V
IN
from 2V to 5V to a regulated 5V ±4% output
voltage. Regulation is achieved by sensing the output
voltage through an internal resistor divider and enabling
the charge pump when the output voltage droops below
the lower trip point of COMP2. When the charge pump is
enabled, a 2-phase, nonoverlapping clock controls the
charge pump switches. Clock 1 closes the S1 switches
which enable the flying capacitors, C1 and C2, to charge
up to the V
IN
voltage. Clock 2 closes the S2 switches which
stack C1 and C2 in series with V
IN
and connect the top
plate of C2 to the output capacitor at V
OUT
. This sequence
of charging and discharging continues at a free-running
frequency of 600kHz (typ) until the output has risen to the
upper trip point of COMP2 and the charge pump is
disabled. When the charge pump is disabled, the LTC1516
draws only 8µA (typ) from V
IN
which provides high
efficiency at low load conditions.
To achieve the highest efficiency over the entire V
IN
range,
the LTC1516 operates as either a doubler or a tripler
depending on V
IN
and output load conditions. COMP1 and
COMP2 determine whether the charge pump is in doubler
mode or tripler mode. COMP1 forces the part into tripler
mode if V
IN
is <2.55V, regardless of output load. When V
IN
is >2.55V, the part will be in doubler mode using only C2
as a flying capacitor. In doubler mode, if the output droops
by 50mV under heavy loads, COMP3 will force the charge
pump into tripler mode until V
OUT
climbs above the upper
trip point of COMP3. Under these V
IN
and load conditions,
the nominal V
OUT
will be approximately 50mV lower than
the no load nominal V
OUT
. This method of sensing V
IN
and
output load results in efficiency greater than 80% with V
IN
between 2.5V and 3V.
In shutdown mode, all circuitry is turned off and the part
draws only leakage current (<1µA) from the V
IN
supply.
V
OUT
is also disconnected from V
IN
. The SHDN pin is a
CMOS input with a threshold of approximately V
IN
/2;
however, the SHDN pin can be driven by logic levels that
exceed the V
IN
voltage. The part enters shutdown mode
when a logic high is applied to the SHDN pin. The SHDN pin
cannot float; it must be driven with a logic high or low.