Datasheet

7
LTC1458/LTC1458L
B11 A
MSB
B11 C
MSB
B0 B
LSB
t
1
t
6
B0 D
LSB
B11 A
CURRENT WORD
t
7
t
2
t
9
t
4
t
3
t
8
CLK
D
IN
D
OUT
CS/LD
t
5
1458 TD
B0 D
PREVIOUS WORD
B11 A
PREVIOUS WORD
B10 A
PREVIOUS WORD
B0 B
PREVIOUS WORD
B11 C
PREVIOUS WORD
B0 D
PREVIOUS WORD
Resolution (n): Resolution is defined as the number of
digital input bits, n. It defines the number of DAC output
states (2
n
) that divide the full-scale range. The resolution
does not imply linearity.
Full-Scale Voltage (V
FS
): This is the output of the DAC
when all bits are set to 1.
Voltage Offset Error (V
OS
): The theoretical voltage at the
output when the DAC is loaded with all zeros. The output
amplifier can have a true negative offset, but because the
part is operated from a single supply, the output cannot go
below zero. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.
DAC CODE
1458 F01
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
Figure 1. Effect of Negative Offset
The offset of the part is measured at the code that corre-
sponds to the maximum offset specification:
V
OS
= V
OUT
– [(Code)(V
FS
)/(2
n
– 1)]
Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.
LSB = (V
FS
– V
OS
)/(2
n
– 1) = (V
FS
– V
OS
)/4095
Nominal LSBs:
LTC1458 LSB = 4.095V/4095 = 1mV
LTC1458L LSB = 2.5V/4095 = 0.610mV
Integral Nonlinearity (INL): End-point INL is the maxi-
mum deviation from a straight line passing through the
end-points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset
specification. The INL error at a given input code is
calculated as follows:
INL = [V
OUT
– V
OS
– (V
FS
– V
OS
)(code/4095)]/LSB
V
OUT
= The output voltage of the DAC measured at
the given input code
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