Datasheet

8
LTC1450/LTC1450L
DIGITAL INTERFACE TRUTH TABLE
U
CLR CSMSB CSLSB WR LDAC FUNCTION
H H L L H Loads the eight LSBs into the input latch
HHL↑H Latches the eight LSBs into the input latch
HH↑L H Latches the eight LSBs into the input latch
H L H L H Loads the four MSBs into the input latch
HLH↑H Latches the four MSBs into the input latch
H ↑ H L H Latches the four MSBs into the input latch
H H H H L Loads the input latch data into the DAC latch
HHHH↑Latches the input latch data into the DAC latch
H L L L L Loads input data into DAC latches (latches transparent)
HLLL↑Latches input data into DAC latches
L X X X X All zeros loaded into input and DAC latches
TIMING DIAGRAM
 WUW
BLOCK DIAGRAM
W
CSMSB
WR
LDAC
LTC1450/50L • TD01
t
CS
CSLSB
DATA
t
CS
t
WR
t
WR
t
CWS
t
CWH
t
DWS
t
LDAC
DAC UPDATE
t
DWH
DATA VALID DATA VALID
–
+
REFERENCE
LTC1450: 2.048V
LTC1450L: 1.22V
DAC
12-BIT DAC LATCH
D11
(MSB) D10 D9 D8
D6
D4 D2
D0
(LSB)D7
D5
D3 D1

UPPER 4-BIT
INPUT LATCH
POWER-ON
RESET
LOWER 8-BIT
INPUT LATCH
LDAC
CLR
CSMSB
WR
CSLSB
REFOUTV
CC
20 19 18 17 22
21
16
456789101112131415
24
23
3
1
2
REFHI REFLO X1/X 2
V
OUT
GND
LTC1450/50L • BD