Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - DA converter (DAC) SSOP 24

LTC1450/LTC1450L

Parallel Input, 12-Bit

Rail-to-Rail Micropower

DACs in SSOP

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Guaranteed Monotonic

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Buffered True Rail-to-Rail Voltage Output

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12-Bit Resolution

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3V Operation (LTC1450L) I

: 250µA Typ

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5V Operation (LTC1450) I

: 400µA Typ

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Parallel 12-Bit or 8 + 4-Bit Double Buffered

Digital Input

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Internal Reference

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Output Buffer Configurable to Gain of 1 or 2

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Configurable as a Multiplying DAC

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Internal Power-On Reset

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Maximum DNL Error: 0.5LSB

The LTC

1450/LTC1450L are complete single supply, rail-

to-rail voltage output, 12-bit digital-to-analog converters

(DACs) in a 24-pin SSOP or PDIP package. They include an

output buffer amplifier, reference and a double buffered

parallel digital interface.

The LTC1450 operates from a 4.5V to 5.5V supply. The

output can be pin strapped for 4.095V or 2.048V full-scale.

It has a 2.048V internal reference.

The LTC1450L operates from a 2.7V to 5.5V supply. The

output can be pin strapped for 2.5V or 1.22V full-scale. It

has a 1.22V internal reference.

The LTC1450/LTC1450L offer true stand-alone perfor-

mance. In addition, the reference output, high and low

reference inputs and gain setting resistor are brought to

pins for maximum flexibility.

FEATURES

DESCRIPTION

, LTC and LT are registered trademarks of Linear Technology Corporation.

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Digital Calibration

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Industrial Process Control

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Automatic Test Equipment

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Arbitrary Function Generators

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Battery-Powered Data Conversion Products

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Feedback Control Loops and Gain Control

APPLICATIONS

TYPICAL APPLICATION

REFLOGND

LTC1450: 

0V TO 4.095V

LTC1450L: 

0V TO 2.5V

LTC1450: 5V

LTC1450L: 3V TO 5V

12-BIT

DAC

REFHI

REFOUT

X1/X2

LTC1450

LTC1450L

1450/50L TA01

OUT

UPPER

4-BIT

INPUT

LATCH

D11 (MSB)

DATA IN FROM

MICROPROCESSOR

DATA BUS

FROM

MICROPROCESSOR

DECODE LOGIC

FROM 

SYSTEM RESET

D0 (LSB)

–

REFERENCE

LTC1450: 2.048V

LTC1450L: 1.22V

12-BIT

DAC

LATCH

POWER-ON

RESET

LDAC

CLR

CSMSB

CSLSB

LOWER

8-BIT

INPUT

LATCH

CODE

DNL ERROR (LSB)

0.5

0.0

–0.5

1024 2048 2560

1450/50L TA02

512 1536 3072 3584

4095

Differential Nonlinearity

vs Input Code

Summary of content (16 pages)

PAGE 1
LTC1450/LTC1450L Parallel Input, 12-Bit Rail-to-Rail Micropower DACs in SSOP DESCRIPTION U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1450/LTC1450L are complete single supply, railto-rail voltage output, 12-bit digital-to-analog converters (DACs) in a 24-pin SSOP or PDIP package. They include an output buffer amplifier, reference and a double buffered parallel digital interface.
PAGE 2
LTC1450/LTC1450L U W U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION VCC to GND .............................................. – 0.5V to 7.5V Logic Inputs to GND ................................ – 0.5V to 7.5V VOUT .............................................. – 0.5V to VCC + 0.5V REFOUT, REFLO, REFHI, X1/X2 ..... – 0.5V to VCC + 0.5V Maximum Junction Temperature .......................... 125°C Operating Temperature Range Commercial ...........................................
PAGE 3
LTC1450/LTC1450L ELECTRICAL CHARACTERISTICS VCC = 4.5V to 5.5V (LTC1450), 2.7V to 5.5V (LTC1450L), VOUT unloaded, REFOUT = REFHI, REFLO = GND = X1/X2, TA = TMIN to TMAX, unless otherwise noted.
PAGE 4
LTC1450/LTC1450L ELECTRICAL CHARACTERISTICS VCC = 4.5V to 5.5V (LTC1450), VCC = 2.7V to 3.6V (LTC1450L), TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Switching Characteristics (Note 5) tCS CS (MSB or LSB) Pulse Width ● 40 ns tWR WR Pulse Width ● 40 ns tCWS CS to WR Setup ● 0 ns tCWH CS to WR Hold ● 0 ns tDWS Data Valid to WR Setup VCC = 4.5V to 5.5V (LTC1450) VCC = 2.7V to 3.
PAGE 5
LTC1450/LTC1450L U W TYPICAL PERFORMANCE CHARACTERISTICS 4.5 1600 VCC = 3V ALL LOGIC INPUTS TIED TOGETHER 800 600 FULL SCALE RL TIED TO GND 3.5 1200 1000 1000 4.0 OUTPUT SWING (V) SUPPLY CURRENT (µA) 1400 400 3.0 2.5 VCC = 5V 2.0 1.5 1.0 200 0 LTC1450 Pull-Down Voltage vs Output Sink Current Capability LTC1450 Output Swing vs Load Resistance ZERO SCALE RL TIED TO VCC 0.5 OUTPUT PULL-DOWN VOLTAGE (mV) LTC1450L Supply Current vs Logic Input Voltage 0 0 10 0.3 0.6 0.9 1.2 1.5 1.8 2.
PAGE 6
LTC1450/LTC1450L U W TYPICAL PERFORMANCE CHARACTERISTICS LTC1450 Midscale Transition Data = 2048 to 2047 LTC1450 Large-Scale Settling (Rising) LTC1450 Large-Scale Settling (Falling) DATA INPUTS RISING EDGE 20mV/DIV VOUT DATA INPUTS FALLING EDGE 5V 5V 0V 0V 4V 4V 3V 2V LDAC 3V VOUT NO LOAD 2V 5V 1V 1V 0V 0V 0V 500ns/DIV 2µs/DIV 2µs/DIV 1450/50L G13 1450/50L G14 Output Voltage Full-Scale Settling 0V DATA IN 000H TO FFFH 1450/50L G15 Output Voltage Zero-Scale Settling 5V 5V VO
PAGE 7
LTC1450/LTC1450L U U U PIN FUNCTIONS WR (Pin 1): Write Input (Active Low). Used with CSMSB and/or CSLSB to load data into the input latches. While WR and CSMSB and/or CSLSB are held low the enabled input latches are transparent. The rising edge of WR will latch data into all input latches. CSLSB (Pin 2): Chip Select Least Significant Byte (Active Low). Used with WR to load data into the eight LSB input latches. While WR and CSLSB are held low the eight LSB input latches are transparent.
PAGE 8
LTC1450/LTC1450L U DIGITAL INTERFACE TRUTH TABLE CLR CSMSB CSLSB WR LDAC H H H H H H H H H H L H H H L L ↑ H H L L X L L ↑ H H H H H L L X L ↑ L L ↑ L H H L L X H H H H H H L ↑ L ↑ X FUNCTION Loads the eight LSBs into the input latch Latches the eight LSBs into the input latch Latches the eight LSBs into the input latch Loads the four MSBs into the input latch Latches the four MSBs into the input latch Latches the four MSBs into the input latch Loads the input latch data into the DAC latch Latch
PAGE 9
LTC1450/LTC1450L U U DEFI ITIO S Resolution (n): Resolution is defined as the number of digital input bits (n). It defines the number of DAC output states (2n) that divide the full-scale range. The resolution does not imply linearity. Full-Scale Voltage (VFS): This is the output of the DAC when all bits are set to 1. Voltage Offset Error (VOS): The theoretical voltage at the output when the DAC is loaded with all zeros.
PAGE 10
LTC1450/LTC1450L U OPERATION Parallel Interface The data on the input of the DAC is loaded into the DAC’s input latches when Chip Select (CSLSB and/or CSMSB) and WR are at a logic low. The data that is loaded into the input latches will depend on which of the Chip Selects are at a logic low (see Digital Interface Truth Table). If WR and CSLSB are both low and CSMSB is high, then only data on the eight LSBs (D0 to D7) is loaded into the input latches.
PAGE 11
LTC1450/LTC1450L U TYPICAL APPLICATIONS N Filter VREF to Lower Output Noise (0.18mVRMS at VOUT) 5V 0.1µF DIN FROM µP DATA BUS 10Ω 4.7µF DATA (0:11) VCC REFOUT REFHI CSLSB CSMSB FROM µP AND DECODE LOGIC LTC1450 LTC1450L WR VOUT X1/X2 LDAC FROM SYSTEM RESET OUTPUT CLR GND REFLO LTC1450/50L • TA03 Digitally Programmable Noninverting Amplifier LTC1450: VIN = 0V TO 2.048V (VCC = 4.5V TO 5V) LTC1450L: VIN = 0V TO 1.22V (VCC = 2.7V TO 5.5V) LTC1450L: VIN = 0V TO 2.048V (VCC = 4.5V TO 5.
PAGE 12
LTC1450/LTC1450L U TYPICAL APPLICATIONS N Bipolar Output 12-Bit DAC 5V 10k VREF 5V 3 0.1µF DATA (0:11) VCC 6 LT ®1097 10k 2 DIN FROM µP DATA BUS 7 + – 4 REFOUT REFLO* VOUT – 2.048V TO 2.047V (1mV/LSB) – 5V CSLSB 2.047V CSMSB FROM µP AND DECODE LOGIC LTC1450 VOUT WR X1/X2 LDAC FROM SYSTEM RESET CLR GND 10k VDAC 10k VOUT VOUT = 2.048 + REFHI* ( ) 2048 4095 DIN – 2.048V DIN – 4096 4.
PAGE 13
LTC1450/LTC1450L U TYPICAL APPLICATIONS N 4-Quadrant Multiplying DAC Application Table 1. Binary Code Table for 4-Quadrant, Multiplying DAC Application This application shows the LTC1450L configured as a single supply 4-quadrant multiplying DAC. It uses a 5V supply and only one external component, a 5k resistor tied from REFOUT to ground. (The LTC1450 can be used in a similar fashion.
PAGE 14
LTC1450/LTC1450L U PACKAGE DESCRIPTION Dimensions in Inches (millimeters) unless otherwise noted. G Package 24-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 0.318 – 0.328* (8.07 – 8.33) 24 23 22 21 20 19 18 17 16 15 14 13 0.301 – 0.311 (7.65 – 7.90) 1 2 3 4 5 6 7 8 9 10 11 12 0.205 – 0.212** (5.20 – 5.38) 0.068 – 0.078 (1.73 – 1.99) 0° – 8° 0.005 – 0.009 (0.13 – 0.22) 0.022 – 0.037 (0.55 – 0.95) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.
PAGE 15
LTC1450/LTC1450L U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N Package 24-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 1.265* (32.131) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 0.255 ± 0.015* (6.477 ± 0.381) 0.300 – 0.325 (7.620 – 8.255) 0.130 ± 0.005 (3.302 ± 0.127) 0.045 – 0.065 (1.143 – 1.651) 0.015 (0.381) MIN 0.009 – 0.015 (0.229 – 0.381) 0.125 (3.175) MIN 0.005 (0.127) MIN +0.635 8.255 0.100 ± 0.010 –0.
PAGE 16
LTC1450/LTC1450L RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1257 Complete Serial I/O VOUT 12-Bit DAC 5V to 15V Single Supply in 8-Pin SO and PDIP LTC1451/LTC1452/LTC1453 Complete Serial I/O VOUT 12-Bit DACs 3V/5V Single Supply, Rail-to-Rail in 8-Pin SO and PDIP LTC1446/LTC1446L Dual 12-Bit VOUT DACs in SO-8 Package LTC1446: VCC = 4.5V TO 5.5V, VOUT = 0V TO 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.