Datasheet

3
LTC1433/LTC1434
ELECTRICAL CHARACTERISTICS
T
A
= 25°C, V
IN
= 10V, V
RUN/SS
= 5V, unless otherwise noted.
The ● denotes specifications which apply over the specified temperature
range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: C-grade device specifications are guaranteed over the 0°C to 70°C
temperature range. In addition, C-grade device specifications are assured
over the – 40°C to 85°C temperature range by design or correlation, but
are not production tested.
Note 3: I-grade device specifications are guaranteed over the – 40°C to
85°C temperature range by design, testing or correlation.
Note 4: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
LTC1433/LTC1434: T
J
= T
A
+ (P
D
)(150°C/W)
Note 5: The LTC1433/LTC1434 are tested in a feedback loop which servos
V
OSENSE
to the feedback point for the error amplifier (V
ITH
= 1.19V).
Note 6: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 7: Oscillator frequency is tested by measuring the C
OSC
charge and
discharge currents and applying the formula:
f
OSC
(kHz) =
+
–1
8.4(10
8
)
C
OSC
(pF) + 11
()
1
I
CHG
()
1
I
DIS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
PROG
V
PROG
Input Current 0.5V > V
PROG
–4 –10 µA
V
IN
– 0.5V < V
PROG
< V
IN
4 10 µA
Main Control Loop
I
Q
Input DC Supply Current (Note 6)
Normal Mode 3.6V < V
IN
< 13V 470 µA
Shutdown, Reference Alive V
RUN/SS
= 0V, 3.6V < V
IN
< 13V, LBI > 0.9V 35 70 µA
Complete Shutdown V
RUN/SS
= 0V, 3.6V < V
IN
< 13V, LBI ≤ 0.48V 15 30 µA
V
RUN/SS
RUN/SS Threshold ● 0.8 1.3 2 V
I
RUN/SS
Soft Start Current Source V
RUN/SS
= 0V 1.2 3 4.5 µA
Oscillator and Phase-Locked Loop
f
OSC
Oscillator Frequency C
OSC
= 100pF (Note 7) 112 125 142 kHz
V
CO
High V
PLL LPF
= 2.4V 200 240 kHz
R
PLLIN
PLL Input Resistance 50 kΩ
I
PLL LPF
Phase Detector Output Current
Sinking Capability f
PLLIN
< f
OSC
10 15 20 µA
Sourcing Capability f
PLLIN
> f
OSC
10 15 20 µA
Power-On Reset
V
SATPOR
POR Saturation Voltage I
POR
= 1.6mA, V
OSENSE
= 1V, V
PROG
Open 0.6 1.0 V
I
LPOR
POR Leakage V
POR
= 10V, V
OSENSE
= 1.2V, V
PROG
Open 0.2 1.0 µA
V
TRPOR
POR Trip Voltage from Regulated V
PROG
Pin Open, V
OSENSE
Ramping Negative –11 –7.5 –4 %
Output
t
DPOR
POR Delay V
PROG
Pin Open 65536 Cycles
Low-Battery Comparator
V
SATLBO
LBO Saturation Voltage I
LBO
= 1.6mA, V
LBI
= 1.1V 0.6 1.0 V
I
LLBO
LBO Leakage V
LBO
= 10V, V
LBI
= 1.4V 0.01 1.0 µA
V
TRLBI
LBI Trip Voltage High to Low Transition on LBO 1.16 1.19 1.22 V
V
HYSTLB
Low-Battery Comparator Hysteresis 40 mV
V
SDLB
Low-Battery Shutdown Trip Point 0.74 V
I
INLBI
LBI Input Current V
LBI
= 1.19V 1 50 nA
P-Channel Power FETs Characteristics
R
SMFET
R
DS(ON)
of Small FET I
SSW
= 15mA 3.3 4.1 Ω
R
BIGFET
R
DS(ON)
of Big FET I
BSW
= 150mA 0.8 1.2 Ω
I
LSSW
Small FET Leakage V
RUN/SS
= 0V ● 7 1000 nA
I
LBSW
Big FET Leakage V
RUN/SS
= 0V ● 5 1000 nA