Datasheet

5
LTC1427-50
PIN FUNCTIONS
UUU
SHDN (Pin 1): Shutdown. A logic low puts the chip into
shutdown mode. In shutdown, the digital settings for the
DAC are retained. On release from shutdown, the previ-
ously programmed value for I
OUT
is reinstated.
AD1, AD0 (Pins 2, 3): Address Selection Pins. Tie these
two pins to either V
CC
or GND to select one of four SMBus
addresses to which the LTC1427-50 will respond.
GND (Pin 4): Ground. Ground should be tied directly to a
ground plane.
SDA (Pin 5): SMBus Bidirectional Data Input/Digital Out-
put. This pin is an open-drain output and requires a pull-
up resistor or current source to V
CC
. Data is shifted into the
SDA pin and acknowledged by the SDA pin.
SCL (Pin 6): SMBus Clock Input. Data is shifted into the
SDA pin at the rising edges of the SCL clock during data
transfer.
I
OUT
(Pin 7): DAC Current Output.
V
CC
(Pin 8): Voltage Supply. This supply must be kept free
from noise and ripple by bypassing directly to the ground
plane.
SMBUS
INTERFACE
3-BIT
LATCH
REGISTER A
SCL
SDA
AD0
AD1
EN1
10-BIT
LATCH
10-BIT
CURRENT
DAC
1-BIT LATCH
VOLTAGE
REFERENCE
REGISTER C
REGISTER B
31
2
10
8
EN2
EN2
POWER-ON
RESET
SHDN
SHDN SD
SD
1427 BD
R
ADJ
I
OUT
SD
BLOCK DIAGRAM
W
FU CTIO TABLES
U U
AD1 AD0 SMBus Address Location DAC Power-Up Value Application
L L 0101101 Zero-Scale CCFL Backlight Control
L H 0101111 Zero-Scale General Purpose
H L 0101110 Zero-Scale General Purpose
H H 0101100 Midscale LCD Contrast Control