Datasheet

9
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
WUU
U
PWRGD and RESET
The LTC1421 uses a 1.232V bandgap reference, internal
resistive divider and a precision voltage comparator to
monitor V
OUTLO
(Figure 6).
The reset threshold voltage for V
OUTLO
is determined by
the FB pin connection as summarized in Table 1.
When V
OUTLO
drops below its reset threshold, the com-
parator output goes high, and PWRGD is immediately
pulled low (time point 2). After a 32µs delay, RESET is
pulled low. The RESET delay allows the PWRGD signal to
be used as an early warning that a reset is about to occur.
If the PWRGD signal is used as a interrupt input to a
microprocessor, a short power-down routine can be run
before the reset occurs.
If V
OUTLO
rises above the reset threshold for less than
200ms, the PWRGD output will trip, but the RESET output is
not affected (time point 3). If V
OUTLO
drops below the reset
threshold for less than 32µs, the PWRGD output will trip, but
again the RESET output will not be affected (time point 5).
Voltage Comparator
The uncommitted voltage comparator (COMP2) can be
used to monitor output voltages other than V
OUTLO
. Figure
8a shows how the comparator can be used to monitor a
12V supply (V
OUTHI
), while the 5V supply (V
OUTLO
) gener-
ates a reset when it dips below 4.65V. When the 12V
supply drops below 10.8V, COMPOUT will pull low. The FB
pin is left floating.
Figure 8b shows how the comparator can be used to
monitor the 5V supply (V
OUTHI
) while the 3.3V supply
(V
OUTLO
) generates a reset when it dips below 2.9V. When
the 5V supply drops below 4.65V, COMPOUT will pull low.
The FB pin is tied to V
OUTLO
.
Figure 6. Supply Monitor Block Diagram
–
+
V
CCLO
V
CCLO
V
OUTLO
FB
1421 F06
1.232V
20µA
20µA
26.7k
PWRGD
RESET
COMP1
RESET
TIMING
REF
73.5k
71.5k
V
OUTLO
PWRGD
RESET
32µs
V2 V2 V2 V2
V1
V1V1
12345
200ms
<200ms 200ms
1421 F07
<32µs
Table 1
FEEDBACK PIN V
OUTLO
RESET VOLTAGE
Floating 4.65V
V
OUTLO
2.90V
GND 5.88V
When the V
OUTLO
voltage rises above its reset threshold
voltage, the comparator output goes low, and PWRGD is
immediately pulled high to V
CCLO
by a weak pull-up
current source or external resistor (Figure 7, time points
1 and 4). After a 200ms delay, RESET is pulled high. The
weak pull-up current source to V
CCLO
on PWRGD and
RESET have a series diode so the pins can be pulled above
V
CCLO
by an external pull-up resistor without forcing
current back into V
CCLO
.
Figure 7. Power Monitor Waveforms Figure 8a. Monitor 12V, Reset 5V at 4.65V
1421 F08a
10k
5%
107k
1%
13.7k
1%
5V 12V
–
+
–
+
V
CCLO
V
CCLO
1.232V
LTC1421
20µA
20µA
8
14
13
15
11
16
20
26.7k
COMP1
COMP2
RESET
TIMING
73.5k
107k
1%
6
7
71.5k