Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SOIC 28

LTC1419

1419fb

14-Bit, 800ksps Sampling

A/D Converter with Shutdown

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Sample Rate: 800ksps

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Power Dissipation: 150mW

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81.5dB S/(N + D) and 93dB THD

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No Missing Codes

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No Pipeline Delay

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Nap and Sleep Shutdown Modes

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Operates with 2.5V Internal 15ppm/°C

Reference or External Reference

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True Differential Inputs Reject Common Mode Noise

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20MHz Full-Power Bandwidth Sampling

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Bipolar Input Range: ±2.5V

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28-Pin SSOP and SO Packages

The LTC

1419 is a 1µs, 800ksps, 14-bit sampling

A/D converter that draws only 150mW from ±5V supplies.

This easy-to-use device includes a high dynamic range

sample-and-hold and a precision reference. Two digitally

selectable power shutdown modes provide flexibility for

low power systems.

The LTC1419 has a full-scale input range of ±2.5V. Out-

standing AC performance includes 81.5dB S/(N + D) and

93dB THD with a 100kHz input; 80dB S/(N + D) and 86dB

THD at the Nyquist input frequency of 400kHz.

The unique differential input sample-and-hold can acquire

single-ended or differential input signals up to its 20MHz

bandwidth. The 60dB common mode rejection allows

users to eliminate ground loops and common mode noise

by measuring signals differentially from the source.

The ADC has a µP compatible, 14-bit parallel output port.

There is no pipeline delay in the conversion results. A

separate convert start input and data ready signal (BUSY)

ease connections to FIFOs, DSPs and microprocessors.

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Telecommunications

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Digital Signal Processing

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Multiplexed Data Acquisition Systems

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High Speed Data Acquisition

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Spectrum Analysis

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Imaging Systems

–A

REF

REFCOMP

AGND

D13(MSB)

D12

D11

D10

DGND

BUSY

CONVST

SHDN

LTC1419

1µF

10µF

DIFFERENTIAL

ANALOG INPUT

(–2.5V TO 2.5V)

REF

OUTPUT

2.50V

10µF

–5V

14-BIT

PARALLEL

BUS

µP CONTROL

LINES

1419 TA01

800kHz, 14-Bit Sampling A/D Converter

INPUT FREQUENCY (Hz)

EFFECTIVE BITS

SIGNAL/(NOISE + DISTORTION) (dB)

10k 100k

1419 TA02

1M 2M

SAMPLE

= 800kHz

Effective Bits and Signal-to-(Noise + Distortion)

vs Input Frequency

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents

including 5581252.

Summary of content (20 pages)

PAGE 1
LTC1419 14-Bit, 800ksps Sampling A/D Converter with Shutdown U FEATURES DESCRIPTIO ■ The LTC ®1419 is a 1µs, 800ksps, 14-bit sampling A/D converter that draws only 150mW from ±5V supplies. This easy-to-use device includes a high dynamic range sample-and-hold and a precision reference. Two digitally selectable power shutdown modes provide flexibility for low power systems. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Sample Rate: 800ksps Power Dissipation: 150mW 81.
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LTC1419 W W W AXI U U U W PACKAGE/ORDER I FOR ATIO U ABSOLUTE RATI GS AVDD = VDD = DVDD (Notes 1, 2) ORDER PART NUMBER TOP VIEW Supply Voltage (VDD) ................................................ 6V Negative Supply Voltage (VSS) ............................... – 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3).............................(VSS – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) ......... (VSS – 0.
PAGE 3
LTC1419 W U DY A IC ACCURACY The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP 78 81.5 80.
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LTC1419 U W POWER REQUIRE E TS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER PDIS Power Dissipation Nap Mode Sleep Mode CONDITIONS MIN ● SHDN = 0V, CS = 0V SHDN = 0V, CS = 5V TYP MAX UNITS 150 7.5 1.2 240 12 mW mW mW WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
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LTC1419 U W TYPICAL PERFORMANCE CHARACTERISTICS S/(N + D) vs Input Frequency and Amplitude Signal-to-Noise Ratio vs Input Frequency VIN = 0dB 70 VIN = –20dB 80 60 50 40 30 AMPLITUDE (dB BELOW THE FUNDAMENTAL) 80 SIGNAL-TO -NOISE RATIO (dB) SIGNAL/(NOISE + DISTORTION) (dB) Distortion vs Input Frequency 90 90 VIN = –60dB 20 10 70 60 50 40 30 20 10 0 0 1k 100k 10k INPUT FREQUENCY (Hz) 1k 1M 2M 10k 100k INPUT FREQUENCY (Hz) –10 –20 –30 –40 –50 –60 –70 –80 THD –90 2ND –100 3RD – 110
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LTC1419 U U U PI FU CTIO S + AIN (Pin 1): ±2.5V Positive Analog Input. – AIN (Pin 2): ±2.5V Negative Analog Input. VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with 1µF. REFCOMP (Pin 4): 4.06V Reference Output. Bypass to AGND with 10µF tantalum in parallel with 0.1µF or 10µF ceramic. AGND (Pin 5): Analog Ground. D13 to D6 (Pins 6 to 13): Three-State Data Outputs. The output format is 2’s complement. DGND (Pin 14): Digital Ground for Internal Logic. Tie to AGND.
PAGE 7
LTC1419 TEST CIRCUITS Load Circuits for Output Float Delay Load Circuits for Access Timing 5V 5V 1k 1k DBN DBN DBN 1k CL 1k CL 100pF (A) VOH TO Hi-Z (B) Hi-Z TO VO (A) Hi-Z TO VOH DBN 100pF (B) VOL TO Hi-Z 1419 TC02 1419 TC01 U U W U APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1419 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel output.
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LTC1419 U W U U APPLICATIONS INFORMATION frequencies outside the fundamental. Figure 2 shows a typical LTC1419 FFT plot. 0 fSAMPLE = 800kHz fIN = 99.804687kHz SFDR = 98dB THD = –93.3dB – 20 AMPLITUDE (dB) – 40 Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D) – 1.76]/6.02 where N is the effective number of bits of resolution and S/(N + D) is expressed in dB.
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LTC1419 U W U U AMPLITUDE (dB BELOW THE FUNDAMENTAL) APPLICATIONS INFORMATION 0 (fa + fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: –10 –20 –30 –40 ( ) IMD fa + fb = 20 Log –50 –60 Amplitude at (fa + fb) Amplitude at fa –70 –80 THD –90 Peak Harmonic or Spurious Noise 2ND –100 3RD – 110 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M 1419 G03 Figure 4.
PAGE 10
LTC1419 U W U U APPLICATIONS INFORMATION that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 200ns for full throughput rate). ACQUISITION TIME (µs) 10 LT1223: 100MHz video current feedback amplifier. ±5V to ±15V supplies, 6mA supply current. Low distortion at frequencies above 400kHz. Low noise. Good for AC applications. LT1227: 140MHz video current feedback amplifier.
PAGE 11
LTC1419 U W U U APPLICATIONS INFORMATION many applications. For example, Figure 7 shows a 1000pF capacitor from + AIN to ground and a 100Ω source resistor to limit the input bandwidth to 1.6MHz. The 1000pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion.
PAGE 12
LTC1419 U U W U APPLICATIONS INFORMATION Differential Inputs The LTC1419 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of + AIN – (– AIN) independent of the common mode voltage (see Figure 11a). The common mode rejection holds up to extremely high frequencies, see Figure 10a. The only requirement is that both inputs can not exceed the AVDD or AVSS power supply voltages.
PAGE 13
LTC1419 U U W U APPLICATIONS INFORMATION microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. applied to the – AIN input. For zero offset error, apply – 152µV (i.e., – 0.
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J7 J5 VLOGIC R19 51Ω CS RD SHDN JP5B JP5A HC14 2 JP5C 1 3 R20 1M HC14 U7B C13 10µF 16V C11 1000pF R15 51Ω D15 SS12 R16 51Ω C8 1µF 16V JP2 U7A JP4 DGND C7 1000pF R18 10k R17 10k VOUT GND TABGND 2 4 VIN 3 4 C2 22µF 10V JP3 C4 0.1µF C12 0.1µF C9 10µF 16V VCC C3 VSS 0.1µF U3 V+ LT1363 2 7 – 6 3 + 8 1 V– 4 VCC R14 20Ω VOUT VCC C6 1000pF + VCC NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL RESISTOR VALUES IN OHMS, 1/10W, 5% 2.
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LTC1419 U W U U APPLICATIONS INFORMATION Figure 13b. Suggested Evaluation Circuit Board—Component Side Silkscreen Figure 13c.
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LTC1419 U W U U APPLICATIONS INFORMATION Figure 13d. Suggested Evaluation Circuit Board—Solder Side Layout DIGITAL INTERFACE The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion.
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LTC1419 U U W U APPLICATIONS INFORMATION In slow memory and ROM modes (Figures 19 and 20), CS is tied low and CONVST and RD are tied together. The MPU starts the conversion and reads the output with the RD signal. Conversions are started by the MPU or DSP (no external sample clock). SHDN t3 CONVST 1419 F14b Figure 14b. SHDN to CONVST Wake-Up Timing In slow memory mode, the processor applies a logic low to RD (= CONVST), starting the conversion. BUSY goes low, forcing the processor into a WAIT state.
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LTC1419 U U W U APPLICATIONS INFORMATION tCONV CS = RD = 0 t8 t5 t13 CONVST t6 t6 t6 BUSY t7 DATA (N – 1) DB13 TO DB0 DATA DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0 1419 F17 Figure 17. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) t13 (SAMPLE N) tCONV t5 CS = 0 t8 CONVST t6 BUSY t9 t 11 t 12 RD t 10 DATA N DB13 TO DB0 DATA 1419 F18 Figure 18. Mode 2. CONVST Starts a Conversion.
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LTC1419 W U U UO APPLICATI S I FOR ATIO t CONV CS = 0 t8 (SAMPLE N) RD = CONVST t6 t 11 BUSY t 10 DATA N DB13 TO DB0 DATA (N – 1) DB13 TO DB0 DATA 1419 F20 Figure 20. ROM Mode Timing U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 10.07 – 10.33* (0.397 – 0.407) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 7.65 – 7.90 (0.301 – 0.311) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 5.20 – 5.38** (0.205 – 0.
PAGE 20
LTC1419 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. SW Package 28-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.697 – 0.712* (17.70 – 18.08) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.394 – 0.419 (10.007 – 10.643) NOTE 1 0.291 – 0.299** (7.391 – 7.595) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.037 – 0.045 (0.940 – 1.143) 0.093 – 0.104 (2.362 – 2.642) 0.010 – 0.029 × 45° (0.254 – 0.737) 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.