Datasheet

19
LTC1417
sn1417 1417fas
APPLICATIONS INFORMATION
WUU
U
Figure 17. Internal Conversion Clock Selected. Data Transferred During Conversion Using
the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT)
D12 D11
D11D12
CAPTURE ON
RISING CLOCK
D13
D10D9D8D7D6D5D4D3D2D1D0
FILL
ZEROS
D13
1
t
2
t
3
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
D13 D13 D12 D11
Hi-Z
Hi-Z
DATA NDATA (N – 1)
(SAMPLE N)
(SAMPLE N + 1)
D
OUT
EXTCLKIN = 5
CLKOUT (= SCLK)
CONVST
t
10
t
CONV
t
5
SAMPLE HOLDHOLD
t
7
t
4
t
8
1417 F17
BUSY (= RD)
t
12
t
11
CLKOUT
(= SCLK)
V
IL
V
OH
V
OL
D
OUT
CAPTURE ON
FALLING CLOCK
LTC1417
BUSY (= RD)
CLKOUT ( = SCLK)
BUSYCONVSTCONVST
RD
SCLK
CLKOUT
D
OUT
1413
12
7
8
9
D
OUT
µP OR DSP
(CONFIGURED
AS SLAVE)
OR
SHIFT
REGISTER
Serial Data Output During a Conversion
Using Internal Clock for Conversion and Data Transfer.
Figure 17 shows data from the previous conversion being
clocked out during the conversion with the LTC1417
internal clock providing both the conversion clock and the
SCLK. The internal clock has been optimized for the fastest
conversion time; consequently, this mode can provide the
best overall speed performance. To select the internal
conversion clock, tie EXTCLKIN (Pin 6) high. The internal
clock appears on CLKOUT (Pin 8) which can be tied to
SCLK (Pin 7) to supply the SCLK.