Datasheet

7
LTC1416
TEST CIRCUITS
1k C
L
C
L
DBN
(A) Hi-Z TO V
OH
AND V
OL
TO V
OH
(B) Hi-Z TO V
OL
AND V
OH
TO V
OL
DBN
1k
5V
1416 TC01
Load Circuits for Access Timing Load Circuits for Output Float Delay
1k 100pF 100pF
DBN
(A) V
OH
TO Hi-Z (B) V
OL
TO Hi-Z
DBN
1k
5V
1416 TC02
APPLICATIONS INFORMATION
WUU
U
CONVERSION DETAILS
The LTC1416 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion, the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun, it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the A
IN
+
and A
IN
–
inputs are
connected to the sample-and-hold capacitors (C
SAMPLE
)
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 400ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the C
SAMPLE
capacitors to ground,
transferring the differential analog input charge onto the
summing junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DAC output balances the A
IN
+
and A
IN
–
input
charges. The SAR contents (a 14-bit data word) which
represents the difference of A
IN
+
and A
IN
–
are loaded into
the 14-bit output latches.
SAMPLE
SAMPLE
C
SAMPLE
+
C
SAMPLE
–
V
DAC
–
V
DAC
+
•
•
•
D13
D0
ZEROING SWITCHES
A
IN
+
C
DAC
+
C
DAC
–
A
IN
–
14
1416 F01
COMP
+
–
HOLD
HOLD
HOLD
HOLD
OUTPUT
LATCH
SAR
Figure 1. Simplified Block Diagram