Datasheet

6
LTC1416
PI FU CTIO S
UU U
A
IN
+
(Pin 1): ±2.5V Positive Analog Input.
A
IN
–
(Pin 2): ±2.5V Negative Analog Input.
V
REF
(Pin 3): 2.5V Reference Output. Bypass to AGND
with 1µF.
REFCOMP (Pin 4): 4.06V Reference Output. Bypass to
AGND with 22µF tantalum in parallel with 0.1µF
ceramic, or 22µF ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 to D0 (Pins 15 to 20): Three-State Data Outputs.
SHDN (Pin 21): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for
nap mode and CS = 1 for sleep mode.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
FU CTIO AL BLOCK DIAGRA
UU W
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): The Chip Select input must be low for the
ADC to recognize CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and
SHDN low select the quick wake-up nap mode. CS high
and SHDN low select sleep mode.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
is valid on the rising edge of BUSY.
V
SS
(Pin 26): –5V Negative Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic, or
10µF ceramic.
DV
DD
(Pin 27): 5V Positive Supply. Tie to Pin 28.
AV
DD
(Pin 28): 5V Positive Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic, or
10µF ceramic.
14-BIT CAPACITIVE DAC
COMPREF AMP
2.5V REF
4k
REFCOMP
(4.06V)
C
SAMPLE
C
SAMPLE
•
•
•
D13
D0
BUSY
CONTROL LOGIC
CSCONVST RDSHDN
INTERNAL
CLOCK
ZEROING SWITCHES
DV
DD
V
SS
AV
DD
A
IN
+
A
IN
–
V
REF
AGND
DGND
14
1416 BD
+
–
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT LATCHES