Datasheet

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LTC1416

Low Power 14-Bit, 400ksps

Sampling ADC

Complete, 70mW, 14-Bit ADC with 80.5dB S/(N + D)

BUSY

CONVST

SHDN

14-BIT ADC

S/H

BUFFER

LTC1416

•

D13 (MSB)

D0 (LSB)

–5V

–

REF

REFCOMP

1µF

22µF

10µF

AGND

1416 TA01

DGND

2.5V

REFERENCE

TIMING

AND

LOGIC

OUTPUT

BUFFERS

INPUT FREQUENCY (Hz)

EFFECTIVE BITS

SIGNAL/(NOISE + DISTORTION) (dB)

10k 100k

1416 TA02

1M 2M

SAMPLE

= 400kHz

NYQUIST

FREQUENCY

Effective Bits and

Signal-to-(Noise + Distortion)

vs Input Frequency

■

Sample Rate: 400ksps

■

Power Dissipation: 70mW

■

Guaranteed

1.5LSB DNL,

2LSB INL (Max)

■

80.5dB S/(N + D) and 93dB THD at 100kHz

■

80dB S/(N + D) and 90dB THD at Nyquist

■

Nap and Sleep Shutdown Modes

■

Operates with Internal or External Reference

■

True Differential Inputs Reject Common Mode Noise

■

15MHz Full Power Bandwidth Sampling

■

±2.5V Bipolar Input Range

■

28-Pin SSOP Package

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

Telecommunications

■

Digital Signal Processing

■

Multiplexed Data Acquisition Systems

■

High Speed Data Acquisition

■

Spectrum Analysis

■

Imaging Systems

The LTC

1416 is a 2.2µs, 400ksps, 14-bit sampling A/D

converter that draws only 70mW from ±5V supplies. This

easy-to-use device includes a high dynamic range sample-

and-hold and a precision reference. Two digitally select-

able power shutdown modes provide flexibility for low

power systems.

The LTC1416’s full-scale input range is ±2.5V. Maximum

DC specifications include ±2LSB INL, ±1.5LSB DNL over

temperature. Outstanding AC performance includes 80.5dB

S/(N + D) and 93dB THD with a 100kHz input, and 80dB

S/(N + D) and 90dB THD at the Nyquist input frequency of

200kHz.

The unique differential input sample-and-hold can ac-

quire single-ended or differential input signals up to its

15MHz bandwidth. The 60dB common mode rejection

allows users to eliminate ground loops and common

mode noise by measuring signals differentially from the

source.

The ADC has a µP compatible, 14-bit parallel output

port. There is no pipeline delay in the conversion

results. A separate convert start input and a data ready

signal (BUSY) ease connections to FIFOs, DSPs and

microprocessors.

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

Summary of content (20 pages)

PAGE 1
LTC1416 Low Power 14-Bit, 400ksps Sampling ADC U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC ®1416 is a 2.2µs, 400ksps, 14-bit sampling A/D converter that draws only 70mW from ±5V supplies. This easy-to-use device includes a high dynamic range sampleand-hold and a precision reference. Two digitally selectable power shutdown modes provide flexibility for low power systems. Sample Rate: 400ksps Power Dissipation: 70mW Guaranteed ± 1.5LSB DNL, ± 2LSB INL (Max) 80.
PAGE 2
LTC1416 W U U W W W AXI U U ABSOLUTE PACKAGE/ORDER I FOR ATIO RATI GS AVDD = DVDD = VDD (Notes 1, 2) ORDER PART NUMBER TOP VIEW Supply Voltage (VDD) ................................................ 6V Negative Supply Voltage (VSS) ............................... – 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) ..........(VSS – 0.
PAGE 3
LTC1416 W U DY A IC ACCURACY The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS S/(N + D) Signal-to-(Noise + Distortion) Ratio 100kHz Input Signal 200kHz Input Signal ● MIN TYP 77 80.
PAGE 4
LTC1416 U W POWER REQUIRE E TS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER ISS Negative Supply Current Nap Mode Sleep Mode SHDN = 0V, CS = 0V SHDN = 0V, CS = 5V Power Dissipation Power Dissipation, Nap Mode Power Dissipation, Sleep Mode SHDN = 0V, CS = 0V SHDN = 0V, CS = 5V PDISS CONDITIONS TYP MAX ● MIN 7 20 15 10 UNITS mA µA µA ● 70 4 0.
PAGE 5
LTC1416 U W TYPICAL PERFORMANCE CHARACTERISTICS S/(N + D) vs Input Frequency and Amplitude AMPLITUDE (dB BELOW THE FUNDAMENTAL) VIN = 0dB 80 80 70 VIN = –20dB 60 50 40 30 VIN = –60dB 20 70 60 50 40 30 20 10 10 0 0 1k 10k 100k INPUT FREQUENCY (Hz) 1k 1M 2M 10k 100k INPUT FREQUENCY (Hz) Spurious-Free Dynamic Range vs Input Frequency –20 –30 –40 –50 –60 –70 –80 –90 1M 2M 1k –50 –60 –70 10k 100k INPUT FREQUENCY (Hz) 1M 2M 1416 G03 Differential Nonlinearity vs Output Code 1.
PAGE 6
LTC1416 U U U PI FU CTIO S AIN+ (Pin 1): ±2.5V Positive Analog Input. AIN– (Pin 2): ±2.5V Negative Analog Input. VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with 1µF. REFCOMP (Pin 4): 4.06V Reference Output. Bypass to AGND with 22µF tantalum in parallel with 0.1µF ceramic, or 22µF ceramic. AGND (Pin 5): Analog Ground. D13 to D6 (Pins 6 to 13): Three-State Data Outputs. DGND (Pin 14): Digital Ground for Internal Logic. Tie to AGND. D5 to D0 (Pins 15 to 20): Three-State Data Outputs.
PAGE 7
LTC1416 TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay 5V 5V 1k 1k DBN DBN DBN 1k CL 1k CL (A) Hi-Z TO VOH AND VOL TO VOH DBN (B) Hi-Z TO VOL AND VOH TO VOL 1416 TC01 (A) VOH TO Hi-Z 100pF 100pF (B) VOL TO Hi-Z 1416 TC02 U U W U APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1416 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel output.
PAGE 8
LTC1416 U W U U APPLICATIONS INFORMATION DYNAMIC PERFORMANCE Signal-to-Noise Ratio The LTC1416 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC1416 FFT plot.
PAGE 9
LTC1416 U U W U APPLICATIONS INFORMATION Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20 log V22 + V32 + V42 + ...Vn2 V1 AMPLITUDE (dB BELOW THE FUNDAMENTAL) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through Nth harmonics.
PAGE 10
LTC1416 U W U U APPLICATIONS INFORMATION Driving the Analog Input The differential analog inputs of the LTC1416 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN– input is grounded). The AIN+ and AIN– inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sampleand-hold circuit.
PAGE 11
LTC1416 U U W U APPLICATIONS INFORMATION Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1416 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 15MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise.
PAGE 12
LTC1416 U U W U APPLICATIONS INFORMATION The VREF pin can be driven with a DAC or other means shown in Figure 9. This is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. The filtering of the internal LTC1416 reference amplifier will limit the bandwidth and settling time of this circuit. A settling time of 5ms should be allowed for after a reference adjustment.
PAGE 13
LTC1416 U W U U APPLICATIONS INFORMATION 0000 0000 00 and 1111 1111 1111 11. For full-scale adjustment, an input voltage of 2.499544V (FS/2 – 1.5LSB) is applied to AIN and R2 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11. 011...111 OUTPUT CODE 011...110 000...001 000...000 111...111 111...110 100...001 BOARD LAYOUT AND BYPASSING 100...000 FS – 1LSB – (FS – 1LSB) INPUT VOLTAGE (AIN+ – AIN–) 1416 F11a Figure 11a.
PAGE 14
LTC1416 U U W U APPLICATIONS INFORMATION 5V 1µF CER 1 AIN+ AVDD 2 AIN– DVDD VREF VSS 3 4 C5 5 6 7 8 9 10 11 12 13 14 COMP BUSY AGND CS CONVST D13 (MSB) RD D12 SHDN D11 D10 D0 LTC1416 D9 D1 D8 D2 D7 D3 D6 D4 DGND D5 2 L1 3 C7 1 –5V 28 27 26 CUK* CONVERTER 25 24 5 23 C8 22µF 10V TANT MICROPROCESSOR/ MICROCONTROLLER INTERFACE 22 21 + 4 7 6 VIN S/S C10 10µF CER VSW U2 LT1373 GND GND S 20 4 NFB VC 8 R4 4.99k 1% 3 1 C12 0.1µF D1 R3 4.99k 19 C9 0.
PAGE 15
LTC1416 U U W U APPLICATIONS INFORMATION 1 AIN+ AIN– ANALOG INPUT CIRCUITRY + – 2 DIGITAL SYSTEM LTC1416 REFCOMP AGND 5 4 VSS 26 22µF 10µF AVDD DVDD DGND 28 27 14 10µF 1416 F13 Figure 13. Power Supply Grounding Practice. traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1416 has differential inputs to minimize noise coupling. Common mode noise on the AIN+ and AIN– leads will be rejected by the input CMRR.
PAGE 16
CLK A– A+ VLOGIC JP5A JP5B JP5C 1 JP2 RD CS 2 C8 1µF 10V 3 3 HC14 U7B C11 1000pF R15 51Ω D15 SS12 R16 51Ω SHDN HC14 U7A JP4 DGND R19 51Ω R18 10k R17 10k VOUT GND TABGND 2 4 VIN LT1121-5 NOTES: UNLESS OTHERWISE SPECIFIED ALL RESISTOR VALUES IN OHMS, 5% J7 J5 AGND J2 J4 GND +VIN 1 U2 4 C2 22µF 10V VREF JP3 C13 22µF 10 V + VCC 4 1 8 R20 1M VCC C9 10µF 10V C3 VSS 0.1µF V– C4 0.1µF U3 7 LT1363 – 6 3 + V+ 2 VOUT VCC C12 0.
PAGE 17
LTC1416 U W U U APPLICATIONS INFORMATION Figure 14b. Suggested Evaluation Circuit Board— Component Side Silkscreen Figure 14c. Suggested Evaluation Circuit Board— Component Side Layout CS t3 SHDN 1416 F15a Figure 15a. CS to SHDN Timing SHDN t4 CONVST 1416 F15b Figure 15b. SHDN to CONVST Wake-Up Timing Figure 14d.
PAGE 18
LTC1416 U U W U APPLICATIONS INFORMATION Shutdown is controlled by Pin 21 (SHDN), the ADC is in shutdown when it is low. The shutdown mode is selected with Pin 20 (CS), low selects nap. starts the conversion and reads the output with the RD signal. Conversions are started by the MPU or DSP (no external sample clock). Timing and Control In slow memory mode, the processor applies a logic low to RD (= CONVST), starting the conversion. BUSY goes low, forcing the processor into a Wait state.
PAGE 19
LTC1416 U U W U APPLICATIONS INFORMATION tCONV CS = RD = 0 t8 t5 t13 CONVST t6 t6 t6 BUSY t7 DATA (N – 1) DB13 TO DB0 DATA DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0 1416 F18 Figure 18. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) t13 (SAMPLE N) tCONV t5 CS = 0 t8 CONVST t6 BUSY t9 t 12 t 11 RD t 10 DATA N DB13 TO DB0 DATA 1416 F19 Figure 19. Mode 2. CONVST Starts a Conversion.
PAGE 20
LTC1416 U U W U APPLICATIONS INFORMATION t CONV CS = 0 t8 (SAMPLE N) RD = CONVST t6 t 11 BUSY t 10 DATA N DB13 TO DB0 DATA (N – 1) DB13 TO DB0 DATA 1416 F21 Figure 21. ROM Mode Timing U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 5.20 – 5.38** (0.205 – 0.212) 1.73 – 1.99 (0.068 – 0.078) 10.07 – 10.33* (0.397 – 0.407) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0° – 8° 0.55 – 0.95 (0.022 – 0.