Datasheet

7
LTC1409
PI FU CTIO S
UU U
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): Chip Select. The input must be low for the
ADC to recognize CONVST and RD inputs.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
valid on the rising edge of BUSY.
V
SS
(Pin 26): –5V Negative Supply. Bypass to AGND
using 10µF tantalum in parallel 0.1µF or 10µF ceramic.
OV
DD
(Pin 27): Positive Supply for Output Drivers. For
5V logic, short to Pin 28. For 3V logic, short to supply
of the logic being driven.
AV
DD
(Pin 28): 5V Positive Supply. Bypass to AGND
10µF tantalum in parallel with 0.1µF or 10µF ceramic.
Load Circuits for Bus Relinquish Time
Load Circuits for Access Timing
1k 100pF 100pF
DBN
DBN
1k
5V
LTC1409 • TC02
1k C
L
C
L
DBN DBN
1k
5V
LTC1409 • TC01
(a) Hi-Z to V
OH
and V
OL
to V
OH
(b) Hi-Z to V
OL
and V
OH
to V
OL
(a) V
OH
to Hi-Z (b) V
OL
to Hi-Z
FU CTIO AL BLOCK DIAGRA
UU W
12-BIT CAPACITIVE DAC
COMPREF AMP
2.5V REF
4k
REFCOMP
(4.06V)
C
SAMPLE
C
SAMPLE
•
•
•
D11
D0
BUSY
CONTROL LOGIC
CSCONVSTRDSHDN
INTERNAL
CLOCK
NAP/SLP
ZEROING SWITCHES
OV
DD
OGND
AV
DD
+A
IN
–A
IN
V
REF
AGND
DGND
12
LTC1409 • BD
+
–
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT LATCHES
TEST CIRCUITS
