Datasheet
LTC1407-1/LTC1407A-1
5
14071fb
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
DD
without latchup.
Note 4: Offset and range specifi cations apply for a single-ended CH0
+
or CH1
+
input with CH0
–
or CH1
–
grounded and using the internal 2.5V
reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defi ned as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defi ned for the voltage difference
between CH0
+
and CH0
–
or CH1
+
and CH1
–
. Performance is specifi ed
with CHO
–
= 1.5V DC while driving CHO
+
and with CH1
–
= 1.5V DC while
driving CH1
+
.
Note 9: The absolute voltage at CH0
+
,
CH0
–
, CH1
+
and CH1
–
must be
within this range.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency per Channel
(Conversion Rate)
l
1.5 MHz
t
THROUGHPUT
Minimum Sampling Period (Conversion + Acquisition Period)
l
667 ns
t
SCK
Clock Period (Note 16)
l
19.6 10000 ns
t
CONV
Conversion Time (Note 6) 32 34 SCLK cycles
t
1
Minimum Positive or Negative SCLK Pulse Width (Note 6) 2 ns
t
2
CONV to SCK Setup Time (Notes 6, 10) 3 10000 ns
t
3
SCK Before CONV (Note 6) 0 ns
t
4
Minimum Positive or Negative CONV Pulse Width (Note 6) 4 ns
t
5
SCK to Sample Mode (Note 6) 4 ns
t
6
CONV to Hold Mode (Notes 6, 11) 1.2 ns
t
7
32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period)
(Notes 6, 7, 13) 45 ns
t
8
Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 6, 12) 8 ns
t
9
SCK to Hi-Z at SDO (Notes 6, 12) 6 ns
t
10
Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns
t
12
V
REF
Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T
A
= 25°C. V
DD
= 3V.
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
32nd rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V
P-P
input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The LTC1407A-1 is measured and specifi ed with 14-bit
Resolution (1LSB = 152µV) and the LTC1407-1 is measured and specifi ed
with 12-bit Resolution (1LSB = 610µV).
Note 18: The sampling capacitor at each input accounts for 4.1pF of the
input capacitance.
Note 19: Full-scale sinewaves are fed into the noninverting inputs while
the inverting inputs are kept at 1.5V DC.