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LTC1407-1/LTC1407A-1

14071fb

BLOCK DIAGRAM

DESCRIPTION

Serial 12-Bit/14-Bit, 3Msps

Simultaneous Sampling

ADCs with Shutdown

The LTC

1407-1/LTC1407A-1 are 12-bit/14-bit, 3Msps

ADCs with two 1.5Msps simultaneously sampled differ-

ential inputs. The devices draw only 4.7mA from a single

3V supply and come in a tiny 10-lead MS package. A sleep

shutdown feature lowers power consumption to 10µW.

The combination of speed, low power and tiny package

makes the LTC1407-1/LTC1407A-1 suitable for high speed,

portable applications.

The LTC1407-1/LTC1407A-1 contain two separate differ-

ential inputs that are sampled simultaneously on the rising

edge of the CONV signal. These two sampled inputs are

then converted at a rate of 1.5Msps per channel.

The 80dB common mode rejection allows users to eliminate

ground loops and common mode noise by measuring

signals differentially from the source.

The devices convert –1.25V to 1.25V bipolar inputs differ-

entially. The absolute voltage swing for CH0

, CH0

–

, CH1

and CH1

–

extends from ground to the supply voltage.

The serial interface sends out the two conversion results in 32

clocks for compatibility with standard serial interfaces.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 6084440, 6522187.

THD, 2nd and 3rd vs Input Frequency

for Differential Input Signals

FEATURES

APPLICATIONS

3Msps Sampling ADC with Two Simultaneous

Differential Inputs

1.5Msps Throughput per Channel

Low Power Dissipation: 14mW (Typ)

3V Single Supply Operation

±1.25V Differential Input Range

Pin Compatible 0V to 2.5V Input Range Version

(LTC1407/LTC1407A)

2.5V Internal Bandgap Reference with External

Overdrive

3-Wire Serial Interface

Sleep (10µW) Shutdown Mode

Nap (3mW) Shutdown Mode

80dB Common Mode Rejection at 100kHz

Tiny 10-Lead MS Package

Telecommunications

Data Acquisition Systems

Uninterrupted Power Supplies

Multiphase Motor Control

I & Q Demodulation

Industrial Radio

–

S & H

–

S & H

GND

EXPOSED PAD

REF

10µF

CH0

–

CH0

CH1

–

CH1

3V10µF

LTC1407A-1

THREE-

STATE

SERIAL

OUTPUT

PORT

MUX

2.5V

REFERENCE

TIMING

LOGIC

SDO

CONV

SCK

1407A1 BD

3Msps

14-BIT ADC

14-BIT LATCH14-BIT LATCH

FREQUENCY (MHz)

0.1

–80

THD, 2ND, 3RD (dB)

–74

–68

–62

–56

11020

14071 TA01b

–86

–92

–98

–104

–50

–44

THD

3RD

2ND

Summary of content (26 pages)

PAGE 1
LTC1407-1/LTC1407A-1 Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown DESCRIPTION FEATURES n n n n n n n n n n n 3Msps Sampling ADC with Two Simultaneous Differential Inputs 1.5Msps Throughput per Channel Low Power Dissipation: 14mW (Typ) 3V Single Supply Operation ±1.25V Differential Input Range Pin Compatible 0V to 2.5V Input Range Version (LTC1407/LTC1407A) 2.
PAGE 2
LTC1407-1/LTC1407A-1 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) TOP VIEW Supply Voltage (VDD) .................................................4V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................. –0.3V to (VDD + 0.3V) Power Dissipation ...............................................100mW Operation Temperature Range LTC1407C-1/LTC1407AC-1 ......................
PAGE 3
LTC1407-1/LTC1407A-1 ANALOG INPUT The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. With internal reference, VDD = 3V.
PAGE 4
LTC1407-1/LTC1407A-1 INTERNAL REFERENCE CHARACTERISTICS PARAMETER CONDITIONS VREF Output Voltage IOUT = 0 TA = 25°C. VDD = 3V. MIN TYP VREF Output Tempco MAX UNITS 2.5 V 15 ppm/°C VREF Line Regulation VDD = 2.7V to 3.6V, VREF = 2.5V 600 μV/V VREF Output Resistance Load Current = 0.5mA 0.2 Ω 2 ms VREF Setting Time DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C.
PAGE 5
LTC1407-1/LTC1407A-1 TIMING CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VDD = 3V.
PAGE 6
LTC1407-1/LTC1407A-1 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, TA = 25°C. Single-ended signals drive +CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1407A-1) 74 11.5 71 11.0 68 10.5 65 10.0 62 9.5 59 9.0 56 8.5 53 1 10 FREQUENCY (MHz) 104 –50 98 –56 92 –62 86 –68 THD –74 3RD –80 2ND 56 50 1 10 FREQUENCY (MHz) 68 11.0 68 10.5 65 10.0 62 9.5 59 56 9.0 56 53 8.5 53 ENOBs (BITS) 71 100 8.0 0.
PAGE 7
LTC1407-1/LTC1407A-1 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, TA = 25°C. Single-ended signals drive +CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1407A-1) 1403kHz Input Summed with 1563kHz Input IMD 4096 Point FFT Plot for Differential Input Signals 0 0 –10 –10 0 –10 –20 –20 –30 –30 –40 –30 –40 –40 –50 –60 –70 –80 MAGNITUDE (dB) –20 MAGNITUDE (dB) MAGNITUDE (dB) 10.
PAGE 8
LTC1407-1/LTC1407A-1 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, TA = 25°C. Single ended signals drive +CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1407A-1) Differential and Integral Linearity vs Conversion Rate SINAD vs Conversion Rate 78 8 7 77 76 5 4 75 MAX INL S/(N+D) (dB) LINEARITY (LSB) 6 3 2 MAX DNL 1 0 –1 74 73 72 MIN DNL 71 MIN INL 70 –2 EXTERNAL VREF = 3.3V, fIN ~ fS/3 EXTERNAL VREF = 3.3V, fIN ~ fS/40 INTERNAL VREF = 2.
PAGE 9
LTC1407-1/LTC1407A-1 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, TA = 25°C (LTC1407-1/LTC1407A-1) Reference Voltage vs Load Current Reference Voltage vs VDD 2.4902 2.4900 2.4900 2.4898 2.4898 VREF (V) VREF (V) 2.4902 2.4896 2.4896 2.4894 2.4894 2.4892 2.4892 2.4890 2.4890 2.6 2.8 3.0 3.2 VDD (V) 3.4 3.6 14071 G26 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (mA) 14071 G27 PIN FUNCTIONS CH0+ (Pin 1): Noninverting Channel 0.
PAGE 10
LTC1407-1/LTC1407A-1 BLOCK DIAGRAM 3V CH0+ 1 + S&H CH0– 2 – MUX CH1+ 4 + S&H CH1– 5 3 10μF – GND 11 LTC1407A-1 THREESTATE SERIAL OUTPUT PORT 8 SDO 10 CONV 9 SCK TIMING LOGIC VREF 6 3Msps 14-BIT ADC VDD 14-BIT LATCH 7 14-BIT LATCH 10μF 2.
PAGE 11
SDO INTERNAL S/H STATUS CONV SCK SDO INTERNAL S/H STATUS CONV SCK t6 t4 34 t6 t4 34 SAMPLE 33 SAMPLE 33 Hi-Z t3 t8 2 3 D11 4 6 HOLD 7 1 Hi-Z t3 2 t8 t2 3 D13 4 8 t1 9 10 11 12 13 14 15 D10 D9 D8 6 HOLD 7 8 t1 D6 D4 9 10 11 12-BIT DATA WORD D5 D3 12 D2 D0 D12 D11 D10 D9 D8 D6 14-BIT DATA WORD D7 D5 D4 X* X* 17 19 t8 20 13 14 15 D3 D2 D1 t9 16 D0 17 19 22 HOLD 23 24 25 26 27 28 29 30 t8 20 D10 21 D9 22 D8
PAGE 12
LTC1407-1/LTC1407A-1 TIMING DIAGRAMS Nap Mode Waveforms SCK t1 CONV NAP Sleep Mode Waveforms SCK t1 t1 CONV NAP SLEEP t12 VREF 1407 TD02 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS SCK to SDO Delay SCK VIH SCK VIH t8 t10 SDO t9 VOH 90% SDO 10% VOL 14071 TD03 14071fb 12
PAGE 13
LTC1407-1/LTC1407A-1 APPLICATIONS INFORMATION DRIVING THE ANALOG INPUT The differential analog inputs of the LTC1407-1/LTC1407A-1 are easy to drive. The inputs may be driven differentially or as a single-ended input (i.e., the CH0– input is AC grounded at VCC /2). All four analog inputs of both differential analog input pairs, CH0+ with CH0– and CH1+ with CH1–, are sampled at the same instant.
PAGE 14
LTC1407-1/LTC1407A-1 APPLICATIONS INFORMATION LT1818/LT1819: 400MHz, 2500V/μs, 9mA, Single/Dual Voltage Mode Operational Ampliﬁer. LT6200: 165MHz GBWP, –85dBc distortion at 1MHz, unity-gain stable, rail-to-rail in and out, 15mA/ampliﬁer, 0.95nV/√Hz. LT6203: 100MHz GBWP, –80dBc distortion at 1MHz, unity-gain stable, rail-to-rail in and out, 3mA/ampliﬁer, 1.9nV/√Hz. components can add distortion. NPO and silvermica type dielectric capacitors have excellent linearity.
PAGE 15
LTC1407-1/LTC1407A-1 APPLICATIONS INFORMATION INTERNAL REFERENCE The LTC1407-1/LTC1407A-1 have an on-chip, temperature compensated, bandgap reference that is factory trimmed near 2.5V to obtain a precise ±1.25V input span. The reference ampliﬁer output VREF, (Pin 3) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1μF or greater. For the best noise performance, a 10μF ceramic or a 10μF tantalum in parallel with a 0.1μF ceramic is recommended.
PAGE 16
LTC1407-1/LTC1407A-1 APPLICATIONS INFORMATION 5V 0 –10 C5 0.1μF C3 1μF – U1 1/2 LT1819 VIN 1.25VP-P MAX R1 51Ω + C6 0.1μF R4 499Ω R5 1k R3 499Ω –5V – U2 1/2 LT1819 + C1 47pF +CH0 OR +CH1 –50 –60 –70 –80 –90 –100 1.5VCM LTC1407A-1 R6 1k C4 1μF MAGNITUDE (dB) –20 –30 –40 R2 51Ω –110 –120 0 185k 371k 556k FREQUENCY (Hz) 741k 14031 F06b C2 47pF –CH0 OR –CH1 1407A F06a Figure 6b.
PAGE 17
LTC1407-1/LTC1407A-1 APPLICATIONS INFORMATION at the LTC1407-1/LTC1407A-1 Exposed Pad. The ground return from the LTC1407-1/LTC1407A-1 Pin 6 to the power supply should be low impedance for noise-free operation. The Exposed Pad of the 10-lead MSE package is also tied to Pin 6 and the LTC1407-1/LTC1407A-1 GND. The Exposed Pad should be soldered on the PC board to reduce ground connection inductance. Digital circuitry grounds must be connected to the digital supply common.
PAGE 18
LTC1407-1/LTC1407A-1 APPLICATIONS INFORMATION Serial Clock Input (SCK) The rising edge of SCK advances the conversion process and also updates each bit in the SDO data stream. After CONV rises, the third rising edge of SCK sends out two sets of 12/14 data bits, with the MSB sent ﬁrst. A simple approach is to generate SCK to drive the LTC1407-1/ LTC1407A-1 ﬁrst and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port.
PAGE 19
LTC1407-1/LTC1407A-1 APPLICATIONS INFORMATION ; ; ; ; ; ; ; ; ; ; ; 12-03-03 ****************************************************************** Files: 014SIAB.ASM -> 1407A Sine wave collection with Serial Port interface bvectors.asm both channels collected in sequence in the same 2k record. s2k14ini.asm Buffered mode 2k buffer size. First element at 1024, last element at 1023, two middles at 2047 and 0000 bipolar mode Works 16 or 64 clock frames.
PAGE 20
LTC1407-1/LTC1407A-1 APPLICATIONS INFORMATION ; ——————— mask and shift input data —————————————— bufull: b = *ar3+ << -0 b = #07FFFh & b b = b ^ #2000h ; load acc b with BSP buffer and shift right -0 ; mask out the TRISTATE bits with #03FFFh ; invert the MSB for bipolar operation *ar2+ = data(#0bh) TC = (@ar2 == #02000h) if (TC) goto start goto bufull ; store B to out buffer and advance AR2 pointer ; output buffer is 2k starting at 1800h ; restart if out buffer is at 1fffh ; ; bsend ; ————————— dumm
PAGE 21
LTC1407-1/LTC1407A-1 APPLICATIONS INFORMATION .title “Vector Table” .mmregs reset nmi trap2 int0 int1 int2 tint brint bxint trint txint int3 hpiint goto #80h nop nop return_enable nop nop nop goto #88h nop nop .
PAGE 22
LTC1407-1/LTC1407A-1 APPLICATIONS INFORMATION .space 24*16 ;68-7F; reserved area ********************************************************************** * (C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996 * ********************************************************************** * * * File: s2k14ini.
PAGE 23
LTC1407-1/LTC1407A-1 APPLICATIONS INFORMATION * 2’ cable from counter to CLK at DUT *No right shift is needed to right justify the input data in the main program * *the two msbs should also be masked * ******************************************************************************************* * Loopback .set NO ;(digital looback mode?) DLB bit Format .set BIT_16 ;(Data format? 16,12,10,8) FO bit IntSync .set NO ;(internal Frame syncs generated?) TXM bit IntCLK .
PAGE 24
LTC1407-1/LTC1407A-1 PACKAGE DESCRIPTION MSE Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1664 Rev C) BOTTOM VIEW OF EXPOSED PAD OPTION 2.794 p 0.102 (.110 p .004) 5.23 (.206) MIN 0.889 p 0.127 (.035 p .005) 1 0.05 REF 10 3.00 p 0.102 (.118 p .004) (NOTE 3) DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 10 9 8 7 6 DETAIL “A” 0o – 6o TYP 1 2 3 4 5 GAUGE PLANE 0.53 p 0.152 (.021 p .006) DETAIL “A” 0.18 (.007) 0.497 p 0.
PAGE 25
LTC1407-1/LTC1407A-1 REVISION HISTORY REV DATE DESCRIPTION B 12/09 Update Pin Conﬁguration (Revision history begins at Rev B) PAGE NUMBER 2 14071fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PAGE 26
LTC1407-1/LTC1407A-1 TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTC1608 16-Bit, 500ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD LTC1609 16-Bit, 250ksps Serial ADC 5V Conﬁgurable Bipolar/Unipolar Inputs LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial ADC 3V, 15mW, Unipolar Inputs, MSOP Package LTC1403-1/LTC1403A-1 12-/14-Bit, 2.