Datasheet

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LTC1405

1405fa

TYPICAL APPLICATION

APPLICATIO S

FEATURES

DESCRIPTIO

12-Bit, 5Msps,

Sampling ADC

The LTC

1405 is a 5Msps, 12-bit sampling A/D converter

that draws only 115mW from either single 5V or dual ±5V

supplies. This easy-to-use device includes a high dynamic

range sample-and-hold, a precision reference and a PGA

input circuit.

The LTC1405 has a flexible input circuit that allows full-scale

input ranges of ±2.048V, ±1.024V and ±0.512V. The input

common mode range is rail-to-rail and a common mode

bias voltage is provided for single supply applications. The

input PGA has a digitally selectable 1x or 2x gain.

Maximum DC specs include ±1LSB INL and ±1LSB DNL

over temperature. Outstanding AC performance includes

71.3dB S/(N + D) and 85dB SFDR at the Nyquist input fre-

quency of 2.5MHz.

The unique differential input sample-and-hold can acquire

single-ended or differential input signals up to its 100MHz

bandwidth. The 75dB common mode rejection allows users

to eliminate ground loops and common mode noise by

measuring signals differentially from the source. A sepa-

rate output logic supply allows direct connection to 3V

components.

■

5Msps Sample Rate

■

Low Power Dissipation: 115mW

■

Single 5V Supply or ±5V Supplies

■

71.3dB S/(N + D) and 85dB SFDR at Nyquist

■

100MHz Full-Power Bandwidth Sampling

■

Input PGA

■

Integral Nonlinearity Error <0.35LSB

■

Differential Nonlinearity <0.25LSB

■

±2.048V, ±1.024V and ±0.512V Bipolar Input Range

■

Out-of-Range Indicator

■

True Differential Inputs with 75dB CMRR

■

Pin-Compatible 10Msps Version (LTC1420)

■

28-Pin Narrow SSOP Package

■

Telecommunications

■

Digital Signal Processing

■

Multiplexed Data Acquisition Systems

■

High Speed Data Acquisition

■

Spectral Analysis

■

Imaging Systems

Typical INL Curve

CODE

0 1024 2048 3072 4096

INL (LSBs)

1405 TA02

1.00

0.75

0.50

0.25

–0.25

–0.50

–0.75

–1.00

DIGITAL CORRECTION

LOGIC

OUTPUT

BUFFERS

1405 TA01

MODE SELECT

S/H

1µF

0V OR –5V

1µF

GAIN

1µF

(PIN 23)

(PIN 7)

1µF

OGND

OPTIONAL 3V

LOGIC SUPPLY

D11 (MSB)

D0 (LSB)

5MHz CLK

SENSE

REF

–A

GND

(PIN 6)

GND

(PIN 24)

GND

(PIN 8)

2.048V

2.5V

REFERENCE

PIPELINED 12-BIT ADC

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Summary of content (20 pages)

PAGE 1
LTC1405 12-Bit, 5Msps, Sampling ADC U FEATURES DESCRIPTIO ■ 5Msps Sample Rate Low Power Dissipation: 115mW Single 5V Supply or ±5V Supplies 71.3dB S/(N + D) and 85dB SFDR at Nyquist 100MHz Full-Power Bandwidth Sampling Input PGA Integral Nonlinearity Error <0.35LSB Differential Nonlinearity <0.25LSB ±2.048V, ±1.024V and ±0.
PAGE 2
LTC1405 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO 0VDD = VDD (Notes 1, 2) TOP VIEW Supply Voltage (VDD) ................................................. 6V Negative Supply Voltage (VSS) ................................ – 6V Total Supply Voltage (VDD to VSS) ........................... 12V Analog Input Voltage (Note 3) ............................. (VSS – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) ............................. (VSS – 0.3V) to (VDD + 0.
PAGE 3
LTC1405 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5) SYMBOL PARAMETER tAP Sample-and-Hold Aperture Delay Time CONDITIONS tjitter Sample-and-Hold Aperture Delay Time Jitter CMRR Analog Input Common Mode Rejection Ratio MIN TYP MAX UNITS – 250 –2.048V < (–AIN = +AIN) < 2.048V ps 0.
PAGE 4
LTC1405 U U DIGITAL I PUTS AND OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5) SYMBOL PARAMETER CONDITIONS IIN Digital Input Current VIN = 0V to VDD CIN Digital Input Capacitance VOH High Level Output Voltage VOL MIN ● 0VDD = 4.75V, IO = –10µA 0VDD = 4.75V, IO = –200µA 0VDD = 2.7V, IO = –10µA 0VDD = 2.
PAGE 5
LTC1405 ELECTRICAL CHARACTERISTICS Note 6: Dynamic specifications are guaranteed for dual supply operation with a single-ended + AIN input and – AIN grounded. For single supply dynamic specifications, refer to the Typical Performance Characteristics. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
PAGE 6
LTC1405 U W TYPICAL PERFORMANCE CHARACTERISTICS SFDR vs Input Frequency, Differential Input –55 DUAL SUPPLIES ±2.048V RANGE GAIN = 1× AIN = 0dBFS –60 –65 –65 –70 –70 –75 –80 –75 –85 –90 –90 –95 –95 –100 –100 10 1 INPUT FREQUENCY (MHz) VREF = 4.096V GAIN = 1× 100 1570 0.1 10 1 INPUT FREQUENCY (MHz) 1405 F07 N CODE 23 0.7 22 0.6 N+1 1420 F09 CMRR vs Input Frequency ISS vs Clock Frequency 90 80 70 0.5 VREF = 2.048V 60 CMRR (dB) VREF = 4.
PAGE 7
LTC1405 U U U PI FU CTIO S + AIN (Pin 1): Positive Analog Input. OGND (Pin 21): Output Logic Ground. Tie to GND. – AIN (Pin 2): Negative Analog Input. OVDD (Pin 22): Positive Supply for the Output Logic. Connect to Pin 23 for 5V logic. If not shorted to Pin 23, bypass to GND with a 1µF ceramic. VCM (Pin 3): 2.5V Reference Output.Optional input common mode for single supply operation. Bypass to GND with a 1µF to 10µF ceramic. SENSE (Pin 4): Reference Programming Pin. Ground selects VREF = 4.096V.
PAGE 8
LTC1405 W FU CTIO AL BLOCK DIAGRA U OPTIONAL 3V LOGIC SUPPLY U 5V VDD (PIN 7) GAIN VDD (PIN 23) OVDD + AIN S/H PIPELINED 12-BIT ADC OF –AIN D11 (MSB) OUTPUT BUFFERS VCM DIGITAL CORRECTION LOGIC MODE SELECT D0 (LSB) SENSE CLK 2.5V REFERENCE VREF 2.
PAGE 9
LTC1405 U W U U APPLICATIO S I FOR ATIO Conversion Details Analog Input Ranges The LTC1405 is a high performance 12-bit A/D converter that operates up to 5Msps. It is a complete solution with an on-chip sample-and-hold, a 12-bit pipelined CMOS ADC, a low drift programmable reference and an input programmable gain amplifier. The digital output is parallel, with a 12-bit two’s complement format and an out-ofrange (overflow) bit.
PAGE 10
LTC1405 U W U U APPLICATIO S I FOR ATIO An external reference or a DAC can be used to drive VREF over a 0V to 5V range (Figures 3a and 3b). The input impedance of the VREF pin is 2kΩ, so a buffer may be required for high accuracy. Driving VREF with a DAC is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio.
PAGE 11
LTC1405 U U W U APPLICATIO S I FOR ATIO Table 2. Comparison of Analog Input Configurations SUPPLIES COUPLING VREF AIN + GAIN AIN – COMMENTS ±5V DC 4.096V 1x ±2.048 0 5V DC 4.096V 2x 2.5 ± 1.024 2.5 Best SINAD, THD for Single Supply Best SNR, THD 5V DC 2.048V 1x 2.5 ± 1.024 2.5 Worse Noise than Above Case 5V DC 4.096V 1x 2.5 ± 2.048 2.5 5V DC 4.096V 1x 0 to 4.096 2.048 Same As Above Best Single Supply Noise, THD Is Not Optimal ±5V AC (Transformer) 4.
PAGE 12
LTC1405 U W U U APPLICATIO S I FOR ATIO Differential Operation The THD and SFDR performance of the LTC1405 can be improved by using a center tap RF transformer to drive the inputs differentially. Though the signal can no longer be DC coupled, the improvement in dynamic performance makes this an attractive solution for some applications. Typical connections for single and dual supply systems are shown in Figures 8a and 8b.
PAGE 13
LTC1405 U W U U APPLICATIO S I FOR ATIO Digital Outputs and Overflow Bit (OF) Figure 10 shows the ideal input/output characteristics for the LTC1405. The output data is two’s complement binary for all input ranges and for both single and dual supply operation. One LSB = VREF/4.096. To create a straight binary output, invert the MSB (D11). The overflow bit (OF) indicates when the analog input is outside the input range of the converter.
PAGE 14
LTC1405 U U W U APPLICATIO S I FOR ATIO connected to this ground plane. All bypass capacitors for the LTC1405 should also be connected to this ground plane (Figure 12). The digital system ground should be connected to the analog ground plane at only one point, near the OGND pin. are present.
PAGE 15
5 4 3 2 J2 (J6) BNC (SMB) 5 4 3 2 J1 (J5) BNC (SMB) 1 2 1 –AIN 2 JP4 R16 51Ω OPT R15 51Ω OPT 1 2 2 2 28 JP6 JP5 26 25 1 2 23 24 1 1 +AIN 21 22 1 AGND 1µF 1µF 19 20 1 GAIN C5 C4 1µF 27 C12 18 17 16 15 1 VDD 1 VSS 1 OVDD D1 MBR0520LT1 E7 E6 E5 E4 E3 E2 1 OGND VCC D8 D9 D3 D2 VREF SENSE VCM –AIN +AIN VSS CLK OF GAIN 1 R19 0Ω 2 R18 1 20Ω 2 C6 470pF U1, LTC1405 AGND DVDD AVDD AGND D11 (MSB) DGND OVDD OGND D0 D10 D7 D4 D1 D6 D5 10
PAGE 16
LTC1405 U W U U APPLICATIO S I FOR ATIO Figure 15. Top Silkscreen Layer for LTC1405/LTC1420 Demo Board Figure 16. Top Layer for LTC1405/LTC1420 Demo Board Figure 17.
PAGE 17
LTC1405 U W U U APPLICATIO S I FOR ATIO Figure 18. Power Plane Layer for LTC1405/LTC1420 Demo Board Figure 19.
PAGE 18
LTC1405 U TYPICAL APPLICATIO Single Supply, 5Msps, 12-Bit ADC with 3V Logic Outputs LTC1405 30Ω ANALOG INPUT (2.5V ± 1.024V) 1 1000pF NPO 2 3 1µF 4 5 1µF 6 7 5V 1µF 8 9 10 11 12 13 14 +AIN GAIN –AIN OF VCM CLK SENSE VSS VREF GND GND VDD VDD OVDD GND OGND D11 D0 D10 D1 D9 D2 D8 D3 D7 D4 D6 D5 28 27 26 5MHz CLOCK 25 24 23 5V 1µF 22 3V 1µF 21 20 19 18 17 0V TO 3V 12-BIT PARALLEL DATA PLUS OVERFLOW 16 15 1405 TA03 Dual Supply, 5Msps, 12-Bit ADC with 71.
PAGE 19
LTC1405 U PACKAGE DESCRIPTIO GN Package 28-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) .386 – .393* (9.804 – 9.982) .045 ±.005 28 27 26 25 24 23 22 21 20 19 18 17 1615 .254 MIN .033 (0.838) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 BSC 1 RECOMMENDED SOLDER PAD LAYOUT .015 ± .004 × 45° (0.38 ± 0.10) .0075 – .0098 (0.19 – 0.25) 2 3 4 5 6 7 8 9 10 11 12 13 14 .0532 – .0688 (1.35 – 1.75) .004 – .0098 (0.102 – 0.
PAGE 20
LTC1405 U TYPICAL APPLICATIO Single 3.3V Supply, 5Msps, 12-Bit ADC LTC1405 ANALOG INPUT (2.048VP-P) + – 15Ω 15Ω 1 1000pF, NPO 2 3 1µF 4 5 1.4MHz BOOST REGULATOR 1µF 4.7µH 3.3V 0.1µF 5V + 7 + 15µF 100k 15µF VIN SHDN 6 0.1µF 1µF SW 8 9 LT1613 SHDN FB GND 10 32.4k 11 12 13 14 +AIN GAIN –AIN OF VCM CLK SENSE VSS VREF GND GND VDD VDD OVDD GND OGND D11 D0 D10 D1 D9 D2 D8 D3 D7 D4 D6 D5 28 27 26 OVERFLOW BIT 5MHz CLOCK 25 24 5V 23 TO PIN 7 1µF 22 3.