Datasheet

17
LTC1404
1404fa
Figure 14. CLK to D
OUT
Delay
APPLICATIONS INFORMATION
WUU
U
CLK
CONV
INTERNAL
S/H STATUS
D
OUT
t
7
t
3
12345678910111213
14
15 16 1 2
t
2
t
6
t
4
t
5
t
8
t
ACQ
SAMPLE SAMPLEHOLD HOLD
REFRDY BIT + 12-BIT DATA WORD
Hi-Z Hi-Z
t
CONV
t
SAMPLE
1404 F13
REFRDY D11 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D10
REFRDY
Figure 13. ADC Digital Timing Diagram
t
10
t
8
V
IH
V
OH
V
OL
D
OUT
CLK
t
9
V
IH
90%
10%
D
OUT
CLK
1404 F14