Datasheet

LTC1403-1/LTC1403A-1
4
14031fc
TIMING CHARACTERISTICS
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
DD
= 3.3V
l
2.4 V
V
IL
Low Level Input Voltage V
DD
= 2.7V
l
0.6 V
I
IN
Digital Input Current V
IN
= 0V to V
DD
l
±10 µA
C
IN
Digital Input Capacitance (Note 20) 5 pF
V
OH
High Level Output Voltage V
DD
= 3V, I
OUT
= –200µA
l
2.5 2.9 V
V
OL
Low Level Output Voltage V
DD
= 2.7V, I
OUT
= 160µA
V
DD
= 2.7V, I
OUT
= 1.6mA
l
0.05
0.10
0.4
V
V
I
OZ
Hi-Z Output Leakage D
OUT
V
OUT
= 0V to V
DD
l
±10 µA
C
OZ
Hi-Z Output Capacitance D
OUT
1 pF
I
SOURCE
Output Short-Circuit Source Current V
OUT
= 0V, V
DD
= 3V 20 mA
I
SINK
Output Short-Circuit Sink Current V
OUT
= V
DD
= 3V 15 mA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 17)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Supply Voltage 2.7 3.6 V
I
DD
Positive Supply Voltage Active Mode
Nap Mode
Sleep Mode (LTC1403-1)
Sleep Mode (LTC1403A-1)
l
l
4.7
1.1
2
2
7
1.5
15
10
mA
mA
µA
µA
P
D
Power Dissipation Active Mode with SCK in Fixed State (Hi or Lo) 12 mW
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
DD
= 3V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency per Channel
(Conversion Rate)
l
2.8 MHz
t
THROUGHPUT
Minimum Sampling Period (Conversion + Acquisition Period)
l
357 ns
t
SCK
Clock Period (Note 16)
l
19.8 10000 ns
t
CONV
Conversion Time (Note 6) 16 18 SCLK cycles
t
1
Minimum Positive or Negative SCLK Pulse Width (Note 6) 2 ns
t
2
CONV to SCK Setup Time
(Notes 6, 10) 3 ns
t
3
Nearest SCK Edge Before CONV (Note 6) 0 ns
t
4
Minimum Positive or Negative CONV Pulse Width (Note 6) 4 ns
t
5
SCK to Sample Mode (Note 6) 4 ns
t
6
CONV to Hold Mode (Notes 6, 11) 1.2 ns
t
7
16th SCK
↑
to CONV
↑
Interval (Affects Acquisition Period)
(Notes 6, 7, 13) 45 ns
t
8
Minimum Delay from SCK to Valid Data
(Notes 6, 12) 8 ns
t
9
SCK to Hi-Z at SDO (Notes 6, 12) 6 ns
t
10
Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns
t
12
V
REF
Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= 3V