Datasheet

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LTC1402

Serial 12-Bit, 2.2Msps

Sampling ADC with Shutdown

■

Sample Rate: 2.2Msps

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72dB S/(N + D) and –89dB THD at Nyquist

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Power Dissipation: 90mW (Typ)

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80MHz Full Power Bandwidth Sampling

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No Missing Codes over Temperature

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Available in 16-Pin Narrow SSOP Package

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Single Supply 5V or ±5V Operation

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Nap Mode with Instant Wake-Up: 15mW

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Sleep Mode: 10µW

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True Differential Inputs Reject Common Mode Noise

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Input Range (1mV/LSB): 0V to 4.096V or ±2.048V

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Internal Reference Can Be Overdriven Externally

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3-Wire Interface to DSPs and Processors (SPI and

MICROWIRE

Compatible)

The LTC

1402 is a 12-bit, 2.2Msps sampling A/D con-

verter. This high performance device includes a high dy-

namic range sample-and-hold and a precision reference.

It operates from a single 5V supply or dual ±5V supplies

and draws only 90mW from 5V.

The versatile differential input offers a unipolar range of

4.096V and a bipolar range of ±2.048V for dual supply

systems where high performance op amps perform best,

eliminating the need for special translation circuitry.

The high common mode rejection allows users to elimi-

nate ground loops and common mode noise by measuring

signals differentially from the source.

Outstanding AC performance includes 72dB S/(N + D) and

–93dB SFDR at the Nyquist input frequency of 1.1MHz

with dual ±5V supplies and –84dB SFDR with a single 5V

supply.

The LTC1402 has two power saving modes: Nap and

Sleep. Nap mode consumes only 15mW of power and can

wake up and convert immediately. In Sleep mode, it

typically consumes 10µW of power. Upon power-up from

Sleep mode, a reference ready (REFRDY) signal is avail-

able in the serial data word to indicate that the reference

has settled and the chip is ready to convert.

The 3-wire serial port allows compact and efficient data

transfer to a wide range of microprocessors, microcon-

trollers and DSPs. A digital output driver power supply pin

allows direct connection to 3V or lower logic.

SAMPLE-

AND-HOLD

OUT

BIP/UNI

CONV

SCK

11211

GAIN

–5V OR 0V

10µF

REF

4.096V

10µF

64k

OUTPUT

BUFFER

1402 TA01

2.048

REFERENCE

TIMING

LOGIC

LTC1402

OGND962 DGND

–

5V 3V OR 5V

AGND114 13AGND2

–

64k

12-BIT ADC

MICROWIRE is a trademark of National Semiconductor Corp.

, LTC and LT are registered trademarks of Linear Technology Corporation.

■ Telecommunications

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High Speed Data and Signal Acquisition

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Digitally Multiplexed Data Acquisition Systems

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Digital Radio Receivers

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Spectrum Analysis

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Low Power and Battery-Operated Systems

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Handheld or Portable Instruments

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Imaging Systems

5 Harmonic THD, 2nd, 3rd and SFDR

vs Input Frequency (Unipolar)

INPUT FREQUENCY (Hz)

–80

THD, SFDR, 2ND 3RD (dB)

–60

–40

1401 G05

–100

–120

–20

–90

–70

–50

–110

–10

–30

THD

SFDR

2ND

3RD

SAMPLE

= 2.22MHz

APPLICATIO S

DESCRIPTIO

FEATURES

BLOCK DIAGRA

Summary of content (24 pages)

PAGE 1
LTC1402 Serial 12-Bit, 2.2Msps Sampling ADC with Shutdown DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Sample Rate: 2.2Msps 72dB S/(N + D) and –89dB THD at Nyquist Power Dissipation: 90mW (Typ) 80MHz Full Power Bandwidth Sampling No Missing Codes over Temperature Available in 16-Pin Narrow SSOP Package Single Supply 5V or ±5V Operation Nap Mode with Instant Wake-Up: 15mW Sleep Mode: 10µW True Differential Inputs Reject Common Mode Noise Input Range (1mV/LSB): 0V to 4.096V or ±2.
PAGE 2
LTC1402 W U U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION AVDD = DVDD = OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 6V Negative Supply Voltage (VSS) ............................... – 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3) .......................... (VSS – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) .......................... (VSS – 0.3V) to (VDD + 0.
PAGE 3
LTC1402 W U DYNAMIC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Bipolar mode with ± 5V supplies and unipolar mode with 5V supply. (Note 5) SYMBOL PARAMETER CONDITIONS S/(N + D) Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal 1.1MHz Input Signal Total Harmonic Distortion 100kHz First 5 Harmonics, Bipolar Mode 1.1MHz First 5 Harmonics, Bipolar Mode 100kHz First 5 Harmonics, Unipolar Mode 1.
PAGE 4
LTC1402 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN VDD Positive Supply Voltage VSS Negative Supply Voltage IDD Positive Supply Current Active Mode Nap Mode Sleep Mode ● ● ISS Negative Supply Current Active, Sleep or Nap Modes with SCK Off ● PD Power Dissipation Active Mode with SCK in Fixed State (Hi or Lo) TYP MAX UNITS 5.25 V 4.
PAGE 5
LTC1402 ELECTRICAL CHARACTERISTICS Note 12: The absolute voltage at AIN+ and AIN– must be within this range. Note 13: If less than 7.3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. Note 14: Not the same as aperture delay. Aperture delay is smaller (2.6ns) because the 0.8ns delay through the sample-and-hold is subtracted from the CONV to Hold mode delay.
PAGE 6
LTC1402 U W TYPICAL PERFOR A CE CHARACTERISTICS (Bipolar Mode Plots Run with Dual ±5V Supplies. Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = – 5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C. Sine Wave Spectrum Plot (Bipolar) ±5V Supply 0.55 FREQUENCY (MHz) 1.11 0 3RD 5TH 0.55 FREQUENCY (MHz) 1.11 1402 G09 3RD 4TH 5TH 6TH 0 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0.55 FREQUENCY (MHz) 2ND 4TH 6TH 0 1.
PAGE 7
LTC1402 U W TYPICAL PERFOR A CE CHARACTERISTICS (Bipolar Mode Plots Run with Dual ±5V Supplies. Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = – 5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C. Differential Nonlinearity vs Output Code (Bipolar) Positive Power Supply Rejection for VREF 1.00 1.00 fSAMPLE = 2.2MHz 4.090 fSAMPLE = 2.2MHz 0.75 0.75 0.50 0.50 0.25 0.25 4.080 4.075 INL (LSB) 4.085 DNL (LSB) INTERNAL REFERENCE VOLTAGE (mV) 4.095 0 0 –0.25 –0.
PAGE 8
LTC1402 U U U PIN FUNCTIONS GAIN (Pin 7): Tie to AGND2 to set the reference voltage to 4.096V or tie to VREF to set the reference voltage to 2.048V. (Note 4) BIP/UNI (Pin 8): Tie to logic low to set the input range to unipolar mode or tie to logic high to set the input range to bipolar mode. (Note 4) OGND (Pin 9): Output Ground for the Output Driver. This pin can be tied to the digital ground of the system. All other ground pins should be tied to the analog ground plane.
PAGE 9
LTC1402 WU W TI I G DIAGRA S t2 t7 t3 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 16 1 2 SCK t4 t5 CONV t6 INTERNAL S/H STATUS t0 SAMPLE HOLD SAMPLE DOUT HOLD t8 t8a Hi-Z DOUT REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION REF D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Hi-Z D0 REF REFRDY BIT + 12-BIT DATA WORD tCONV tTHROUGHPUT 1402 TD01 Nap Mode and Sleep Mode Waveforms SCK t1 t1 CONV NAP SLEEP t12 VREF t11 REFRDY NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS.
PAGE 10
LTC1402 U W U U APPLICATIONS INFORMATION DRIVING THE ANALOG INPUT ACQUISITION TIME (ns) The differential analog inputs of the LTC1402 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN– input is grounded). The AIN+ and AIN– inputs are sampled at the same instant. Any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit.
PAGE 11
LTC1402 U W U U APPLICATIONS INFORMATION LT1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to ±15V supplies. Very high AVOL, 500µV offset and 520ns settling to 0.5LSB for a 4V swing. THD and noise are – 93dB to 40kHz and below 1LSB to 320kHz (AV = 1, 2VP-P into 1kΩ, VS = 5V), making the part excellent for AC applications (to 1/3 Nyquist) where rail-to-rail performance is desired. Quad version is available as LT1631. LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to ±15V supplies.
PAGE 12
LTC1402 U U W U APPLICATIONS INFORMATION INTERNAL REFERENCE The LTC1402 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.048V. It is connected internally to a reference amplifier, see Figure 4. The reference amplifier amplifies the voltage at the VREF pin by 2 to create the required internal reference voltage of 4.096V. This provides buffering for the high speed capacitive DAC.
PAGE 13
LTC1402 U W U U APPLICATIONS INFORMATION 0 –10 AMPLITUDE (dB) – 20 – 30 – 40 – 50 – 60 –70 0.1 1 10 100 FREQUENCY (MHz) 1000 1402 F07 Figure 7. CMRR vs Input Frequency INPUT SPAN VERSUS REFERENCE VOLTAGE The differential input range has a voltage span that equals the difference between the voltage at the reference buffer output VREF at Pin 5, and the voltage at the reference ground AGND2 at Pin 6. The external reference voltage may have any value between 2V and 5V.
PAGE 14
LTC1402 U W U U APPLICATIONS INFORMATION more than 0.25 inch long to the common reference. You may also choose to tie AGND2 (Pin 6) directly to a solid analog ground plane and eliminate all the 10µF capacitors at this pin. The external reference source needs to have enough output drive current for the 2kΩ load at each ADC. FULL-SCALE AND OFFSET ADJUSTMENT 011...111 111...111 011...110 111...110 011...101 111...101 100...010 000...010 100...001 000...001 100...000 – (FS – 1LSB) 000...
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LTC1402 U U W U APPLICATIONS INFORMATION 0000 0000 0000 and 0000 0000 0001. For full-scale adjustment in Figures 10a and 10b, apply an input voltage of 2.0465V (FS – 1.5LSBs) to AIN+ and adjust R5 until the output code flickers between 1111 1111 1110 and 1111 1111 1111. The LTC1402 has differential inputs to minimize noise coupling. Common mode noise on the AIN+ and AIN– leads will be rejected by the input CMRR.
PAGE 16
LTC1402 U W U U APPLICATIONS INFORMATION 15mW. The internal reference remains powered in Nap mode. One or more rising edges at SCK wake up the LTC1402 for service very quickly, and CONV can start an accurate conversion within a clock cycle. Four rising edges at CONV, without any intervening rising edges at SCK, put the LTC1402 in Sleep mode and the power drain drops from 90mW to 10µW. One or more rising edges at SCK wake up the LTC1402 for operation.
PAGE 17
LTC1402 U U W U APPLICATIONS INFORMATION edge of CONV. Please note the delay specification from SCK to a valid DOUT. DOUT is always guaranteed to be valid by the next rising edge of SCK. DIGITAL JITTER AT CONV (PIN 16) In high speed applications, where high amplitude sinewaves above 100kHz are sampled, the CONV signal must have as little jitter as possible (10ps or less). The square wave output of a common crystal clock module usually meets this requirement easily.
PAGE 18
LTC1402 U U W U APPLICATIONS INFORMATION HARDWARE INTERFACE TO TMS320C54x The LTC1402 is a serial output ADC whose interface has been designed for high speed buffered serial ports in fast digital signal processors (DSPs). Figure 14 shows an example of this interface using a TMS320C54X. The buffered serial port in the TMS320C54x has direct access to a 2kB segment of memory. The ADC’s serial data can be collected in two alternating 1kB segments, in real time, at the full 2.
PAGE 19
LTC1402 U W U U APPLICATIONS INFORMATION ; *************************************************************************** ; Files: BSP2KB.ASM -> ; 2kbyte collection into DSKPlus TMS320C542 with Serial Port interface to LTC1402 ; first element at 1024, last element at 1023, two middle elements at 2047 and 0000 ; bipolar mode ; *************************************************************************** .width 160 .length 110 .title “sineb0 BSP in auto buffer mode” .mmregs .setsect “.
PAGE 20
LTC1402 U W U U APPLICATIONS INFORMATION * This is an example of how to initialize the Buffered Serial Port (BSP). * The BSP is initialized to require an external CLK and FSX for * operation. The data format is 16-bits, burst mode, with autobuffering * enabled. * * ***************************************************************************************************** *Timing at BSP pins in DSKPLUS TMS320c542 board with inverters at BCLKR and BFSR.
PAGE 21
LTC1402 U W U U APPLICATIONS INFORMATION ; The vectors in this table can be configured for processing external and ; internal software interrupts. The DSKplus debugger uses four interrupt ; vectors. These are RESET, TRAP2, INT2, and HPIINT. ; * DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER * ; ; All other vector locations are free to use. When programming always be sure ; the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and ; host PC interact.
PAGE 22
LTC1402 U TYPICAL APPLICATION Using Quad Cable Drivers/Receivers in Remote LTC1402 Applications unshielded cable. Using these devices, the LTC1402’s serial data can be transmitted up to 100 feet without data corruption. Because the SCK, CONV and DOUT signals originate at the LTC1402, they arrive at the serial port with similar delays and remain synchronized.
PAGE 23
LTC1402 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.007 – 0.0098 (0.178 – 0.249) 0.009 (0.229) REF 2 3 4 5 6 7 0.053 – 0.068 (1.351 – 1.727) 8 0.004 – 0.0098 (0.102 – 0.249) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.008 – 0.012 (0.
PAGE 24
LTC1402 RELATED PARTS PART NUMBER RESOLUTION SPEED COMMENTS LTC1604 16 333ksps ±2.5V Input Range, ±5V Supply LTC1605 16 100ksps ±10V Input Range, Single 5V Supply LTC1606 16 250ksps ±10V Input Range, Pin-Compatible with LTC1605 LTC1608 16 500ksps ±2.5V Input Range, Pin-Compatible with LTC1604 LTC1414 14 2.2Msps 175mW, 80dB SINAD and 95dB SFDR LTC1419 14 800ksps 150mW, 81.