Datasheet

LTC1400
4
1400fa
DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
The denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C unless otherwise noted. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OL
Low Level Output Voltage V
CC
= 4.75V, I
O
= 160μA
V
CC
= 4.75V, I
O
= 1.6mA
0.05
0.10
0.4
V
V
I
OZ
Hi-Z Output Leakage D
OUT
V
OUT
= 0V to V
CC
±10 μA
C
OZ
Hi-Z Output Capacitance D
OUT
(Note 7) 15 pF
I
SOURCE
Output Source Current V
OUT
= 0V –10 mA
I
SINK
Output Sink Current V
OUT
= V
CC
10 mA
TI I G CHARACTERISTICS
UW
The denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C unless otherwise noted. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency (Note 6)
400 kHz
t
CONV
Conversion Time f
CLK
= 6.4MHz
2.1 μs
t
ACQ
Acquisition Time (Unipolar Mode)
(Bipolar Mode V
SS
= –5V)
(Note 7)
230
200
300
270
ns
ns
f
CLK
CLK Frequency
0.1 6.4 MHz
t
CLK
CLK Pulse Width (Notes 7, 12)
50 ns
t
WK(NAP)
Time to Wake Up from Nap Mode (Note 7) 350 ns
t
1
CLK Pulse Width to Return to Active Mode
50 ns
t
2
CONV to CLK Setup Time
80 ns
t
3
CONV After Leading CLK
0 ns
t
4
CONV Pulse Width (Note 11)
50 ns
t
5
Time from CLK to Sample Mode (Note 7) 80 ns
t
6
Aperture Delay of Sample-and-Hold Jitter < 50ps (Note 7)
45 65 ns
t
7
Minimum Delay Between Conversion (Unipolar Mode)
(Bipolar Mode V
SS
= –5V)
265
235
385
355
ns
ns
t
8
Delay Time, CLK to D
OUT
Valid C
LOAD
= 20pF
40 80 ns
t
9
Delay Time, CLK to D
OUT
Hi-Z C
LOAD
= 20pF
40 80 ns
t
10
Time from Previous Data Remains Valid After CLK C
LOAD
= 20pF
14 25 ns
t
11
Minimum Time between Nap/Sleep Request to Wake Up Request (Notes 7, 12)
50 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When these pin voltages are taken below V
SS
(ground for unipolar
mode) or above V
CC
, they will be clamped by internal diodes. This product
can handle input currents greater than 40mA below V
SS
(ground for
unipolar mode) or above V
CC
without latch-up.
Note 4: When these pin voltages are taken below V
SS
(ground for unipolar
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 40mA below V
SS
(ground for unipolar mode)
without latch-up. These pins are not clamped to V
CC
.
Note 5: V
CC
= 5V, f
SAMPLE
= 400kHz, t
r
= t
f
= 5ns unless otherwise
specified.
Note 6: Recommended operating conditions.
Note 7: Guaranteed by design, not subject to test.
Note 8: Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 9: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 10: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 11: The rising edge of CONV starts a conversion. If CONV returns
low at a bit decision point during the conversion, it can create small errors.
For best performance ensure that CONV returns low either within 120ns
after conversion starts (i.e., before the first bit decision) or after the 14
clock cycle. (Figure 13 Timing Diagram).
Note 12: If this timing specification is not met, the device may not respond
to a request for a conversion. To recover from this condition a NAP
request is required.