Datasheet
7
LTC1390
APPLICATIO S I FOR ATIO
UU W U
TYPICAL APPLICATIONS N
U
Daisy-Chaining Five LTC1390s
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S0
S1
S2
S3
S4
S5
S6
S7
V
+
D
V
–
DATA 2
DATA 1
CS
CLK
GND
ANALOG
INPUTS
LTC1390
A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S0
S1
S2
S3
S4
S5
S6
S7
V
+
D
V
–
DATA 2
DATA 1
CS
CLK
GND
ANALOG
INPUTS
LTC1390
E
V
CC
V
CC
V
CC
47k
V
EE
1
2
3
4
8
7
6
5
V
REF
+IN
–IN
GND
V
CC
CLK
D
OUT
CS
LTC1286
LTC1390 • TA03
V
CC
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S0
S1
S2
S3
S4
S5
S6
S7
V
+
D
V
–
DATA 2
DATA 1
CS
CLK
GND
ANALOG
INPUTS
LTC1390
B
DATA*
CS
CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S0
S1
S2
S3
S4
S5
S6
S7
V
+
D
V
–
DATA 2
DATA 1
CS
CLK
GND
ANALOG
INPUTS
LTC1390
C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S0
S1
S2
S3
S4
S5
S6
S7
V
+
D
V
–
DATA 2
DATA 1
CS
CLK
GND
ANALOG
INPUTS
LTC1390
D
REQUIRES FIVE 4-BIT CHANNEL
SELECTION DATA BYTES
BYPASS CAPACITOR FROM V
+
TO GND AND
V
–
TO GND REQUIRED FOR EACH LTC1390
*
CLK 1 2 3 4
ENA ENBA2 A1 A0 B2 B1 B0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
t
DATA
Hi-Z
NULL
BIT
LTC1390 • F06
5678
CS
DATA
t
SMPL
t
CONV
DIGITAL OUTPUT FROM LTC1286DIGITAL INPUT FROM LTC1390
Figure 6. Timing Diagram for Figure 5