Datasheet

22
LTC1325
wiper on a potentiometer between these two. Table 1
illustrates a complete 6-byte exchange. Note that the first
byte is padded with zeroes to align the A/D data and status
with byte boundaries.
SPCR = (SPIE = 0, SPE = 1, DWOM = 0, MSTR = 1,
CPOL = 0, CPHA = 0, SPR1 = 0, SPR0 = 1)
DDRD = (BIT7 = 0, BIT6 = 0, DDR5 = 1, DDR4 = 1,
DDR3 = 1, DDR2 = 0, DDR1 = 0, DDR0 = 1)
Table 1. 6-Byte Exchange SPI Communication with LTC1325
0
BYTE #1 TX
0
SS
SCK
MOSI
PORTD.0
MISO
0000START MOD0
X
BYTE #1 RX
X XXXXXX
MOD1
BYTE #2 TX
SGL/
DIFF
MSBF DS0 DS1 DS2 DIV0 DIV1
X
BYTE #2 RX
X XXXXXX
DIV2
BYTE #3 TX
DIV3 PS DR0 DR1 DR2 FSCLR TO0
BYTE #3 RX
XX XXXXXX
TO1
BYTE #4 TX
TO2 VR0 VR1 0 0 0 0
X
BYTE #4 RX
X XXX0D9 D8
X
BYTE #5 TX
X XXXXXX
D7
BYTE #5 RX
D6 D5 D4 D3 D2 D1 D0
X
BYTE #6 TX
X XXXXXX
BATP
BYTE #6 RX
BATR FMCV FEVD FHTF FLTF t
0UT
FS
LTC1325 • AI01
CLK
D
IN

CS
D
OUT
68HC11
5V
LTC1325
X = DON’T CARE

idle mode to minimize noise. The microprocessor
should either disregard readings or wait for a second
or so before taking a reading. This is to allow V
CELL
to
decay to the correct cell voltage. The worst case time
constant is 150kΩ(C
F
).
10. Prior to the first START command, the battery divider
setting may be incorrect so that C
F
may charge to a
voltage that causes EDV, BATR or MCV faults. The
worst case time constant is as in (9). The micropro-
cessor should check faults during the transmission of
a START command and resend the START command
again when C
F
has been given enough time to charge
up to the correct value.
MICROPROCESSOR INTERFACES
The LTC1325 can interface directly to either synchronous,
serial or parallel I/O ports of most popular microproces-
sors. With a parallel port, 3 or 4 I/O lines can be pro-
grammed to form a serial link to the LTC1325.
Motorola SPI (68HC11)
The 68HC11 has a dedicated synchronous serial interface
called the Serial Peripheral Interface (SPI) which transfers
data with MSB-first and in 8-bit increments. To communicate
with this microprocessor, the LTC1325 MSBF control bit
should be set to 1. The SPI has four lines: Master In Slave Out
(MISO), Master Out Slave In (MOSI), Serial Clock (SCK) and
Slave Select (SS). The 68HC11 is configured as a Master by
tying the SS line high. A control byte is written to the Serial
Peripheral Control Register (SPCR) to select master mode,
set baud rate and clock timing relationship. Another byte is
written to the Port D Direction Register (DDRD) to set MOSI,
SCK and bit 0 (CS of LTC1325) as outputs. The 68HC11
clocks in data from the LTC1325 simultaneously under the
control of SCK. The microprocessor transmits the LTC1325
command word in 4 bytes. This is followed by 2 more dummy
bytes (with all bits set low) in order to clock in the remaining
LTC1325 ADC and status bits.
This software example allows you to verify communica-
tions with the LTC1325. The command word configures
the LTC1325 to perform an A/D conversion on the general
purpose V
IN
input. V
IN
can be tied to GND or REG or to a
APPLICATIONS INFORMATION
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