Datasheet

18
LTC1325
APPLICATIONS INFORMATION
WUU
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between the V
BAT
and Sense pins and the internal
divider should be set to divide-by-1.
The minimum V
DD
supply must be greater than the
end-of-charge voltage V
EC
times the number of cells
(n) in the battery plus drops across the on-resistance
of the PFET, inductor (V
L
), battery internal resistance
R
INT
and sense resistor R
SENSE
.
Minimum V
DD
should be the greater voltage of the
results from these two equations:
Min V
DD
=I
CHRG
[R
DS(ON)
(P1) + R
SENSE
+
n(R
INT
)] + n(V
EC
) + V
L
or,
Min V
DD
= n(V
EC
) + 1.8V
Assuming V
EC
= 1.6V, the LTC1325 will charge up to
8 cells with a 16V supply. For a higher number of cells,
an external level shifter and regulator are needed.
In some applications, there are other circuits attached
to the charging supply. When the charging supply
(V
DC
) is powered down or removed, the battery may
supply current to these circuits through the PFET body
diode. To prevent this, a blocking diode can be added
in series with V
DC
as shown in the circuit in the Typical
Application section.
3. Inductor L: To minimize losses, the inductor should
have low winding resistance. It should be able to
handle expected peak charging currents without satu-
ration. If the inductor saturates, the charging current
is limited only by the total PFET R
DS(ON)
, inductor
winding resistance, R
SENSE
and V
DD
source resis-
tance. This fault current may be high enough to
damage the battery or cause the maximum power
ratings of the PFET, inductor or R
SENSE
to be ex-
ceeded.
4. Catch Diode D1: The catch diode should have a low
forward drop and fast reverse recovery time to mini-
mize power dissipation. Total power loss is given by:
P
dD1
= V
F
(I
F
) + (V
R
)(f)(t
RR
)(I
F
′)
The LTC1325 has five duty ratio and four V
DAC
settings
giving 20 possible charge rates (for a given value of
R
SENSE
) as shown in the following table. For any
combination of V
DAC
and duty ratio, the average
charging current is given by:
AVG I
CHRG
= V
DAC
(Duty Ratio)/R
SENSE
NORMALIZED
DUTY RATIO
V
DAC
1 1/2 1/4 1/8 1/16
1(VR1 = 1, VR0 = 1) 1 1/2 1/4 1/8 1/16
1/3(VR1 = 1, VR0 = 0) 1/3 1/6 1/12 1/24 1/48
1/5(VR1 = 0, VR0 = 1) 1/5 1/10 l/20 1/40 1/80
1/10(VR1 = 0, VR0 = 0) 1/10 1/20 1/40 1/80 1/160
Note that the table entries give relative charge rates
assuming that the VR1 = 1, VR0 = 1, duty ratio = 1 entry
is equivalent to a 1C charge rate. Therefore, the charge
rate (in C-units) for other VR1, VR0, and duty ratio
settings may be read directly from the table. In gen-
eral, the VR1 = 1, VR0 = 1, duty ratio = 1 entry can be
equivalent to any charge rate, say k times 1C. Then all
entries in the table should be multiplied by k. In
general, V
DAC
and duty ratio settings are changed by
the microprocessor to charge batteries of different
capacities or to alter charge rates when charging the
same battery in several stages. For best accuracy, VR1
and VR0 should be set to 1 where possible.
The power dissipation of the sense resistor varies
between charge, discharge and gas gauge modes and
should be calculated for all three modes. Typically,
dissipation is higher in discharge and gas gauge
modes since batteries can deliver higher currents than
they can be charged with.
In gas gauge mode, the load current supplied by the
battery should not exceed 450mV/R
SENSE
for the gas
gauge to remain linear in response. R
SENSE
should be
low enough to ensure that I
LOAD
(R
SENSE
) does not
fall below ground by more than 1 diode drop.
2. V
DD
Supply: V
DD
should be at least 1.8V above the
maximum battery voltage to prevent a BATP = 0 error
when the LTC1325 is in charge or discharge mode. If
this requirement cannot be met in a specific applica-
tion, an external battery divider should be connected