Datasheet

8
LTC1293/LTC1294/LTC1296
129346fs
W
IDAGRA
B
L
O
C
K
(Pin numbers refer to LTC1294)
Load Circuit for t
dDO
, t
r
and t
f
Load Circuit for t
enSSO
and t
disSSO
D
OUT
1.4V
3kΩ
100pF
TEST POINT
LTC1293 TC02
1.4V
3kΩ
100pF
TEST POINT
LTC1293 TC08
SSO
LT1296
TEST CIRCUITS
On and Off Channel Leakage Current
D
OUT
3k
100pF
TEST POINT
5V t
dis
WAVEFORM 2, t
en
t
dis
WAVEFORM 1
LTC1293 TC05
Load Circuit for t
dis
and t
en
INPUT
SHIFT
REGISTER
SAMPLE
AND
HOLD
12-BIT
CAPACITIVE
DAC
DV
CC
20
ANALOG
INPUT MUX
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
D
OUT
16
CLK
18
CONTROL
AND
TIMING
17
CS
LTC1293 BD
19
15
REF
+
14
DGND
10
V
–
11
AGND
12
REF
–
13
COMP
12-BIT
SAR
OUTPUT
SHIFT
REGISTER
D
IN
AV
CC
5V
A
A
I
OFF
I
ON
POLARITY
OFF
CHANNELS
ON CHANNEL
LTC1293 TC1