Datasheet
15
LTC1293/LTC1294/LTC1296
129346fs
Interfacing to the Parallel Port of the Intel 8051 Family
The Intel 8051 has been chosen to show the interface
between the LTC1293/4/6 and parallel port microproces-
sors. Usually the signals CS, D
IN
and CLK are generated
on three port lines and the D
OUT
signal is read on a fourth
port line. This works very well. One can save a line by tying
the D
IN
and D
OUT
lines together. The 8051 first sends the
start bit and D
IN
to the LTC1294 over the line connected to
P1.2. Then P1.2 is reconfigured as an input and the 8051
reads back the 12-bit A/D result over the same data line.
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
Data Exchange Between LTC1294 and MC68HC11
Motorola SPI (MC68HC11)
The MC68HC11 has been chosen as an example of an MPU
with a dedicated serial port. This MPU transfers data MSB-
first and in 8-bit increments. The D
IN
word sent to the data
register starts the SPI process. With three 8-bit transfers,
the A/D result is read into the MPU. The second 8-bit
transfer clocks B11 through B8 of the A/D conversion
result into the processor. The third 8-bit transfer clocks
the remaining bits B7 through B0 into the MPU. The data
is right justified in the two memory locations. ANDing the
second byte with 0D
HEX
clears the four most significant
bits. This operation was not included in the code. It can
be inserted in the data gathering loop or outside the loop
when the data is processed.
Hardware and Software Interface to Motorola MC68HC11
CS
CLK
D
OUT
MPU
RECEIVED
WORD
LTC1293 TD01
UNI
SGL/
DIFF
ODD/
EVEN
SEL
1
SEL
0
START
MSBF PS
B3B7
B6
B5
B4 B2 B0
B1
B11 B10 B9 B8
D
IN
MPU
TRANSMIT
WORD
BYTE 3 (DUMMY)
BYTE 2
SGL
0
ODD
SEL
0
SEL
1
BYTE 1
XUNI
MSBF
PS
X
X
X
X
00
1
START
X
X
X
XX
X
X
X
BYTE 3
BYTE 2
?
?
?
?
?
BYTE 1
B11?
?
?
0
B10
B8
B9
???
B7
B6
B4
B5 B3
B2
B0
B1
DON'T CARE
LTC1293 TD01a
CLK
D
OUT
LTC1294
CS
ANALOG
INPUTS
DO
SCK
MISO
MC68HC11
D
IN
MOSI
B2 B1
B0
B3
B4
B6
B7 B5
BYTE 1
B10 B9 B8B11
OO
OO
D
OUT
FROM LTC1294 STORED ON MC68HC11 RAM
BYTE 2
LSB
MSB
#62
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