Datasheet

7
LTC1292/LTC1297
12927fb
Load Circuit for t
dis
and t
en
Load Circuit for t
dDO
, t
r
and t
f
On and Off Channel Leakage Current
Voltage Waveforms for D
OUT
Delay Time, t
dDO
W
IDAGRA
B
L
O
C
K
TEST CIRCUITS
Voltage Waveforms for D
OUT
Rise and Fall Times, t
r
, t
f
Voltage Waveforms for t
dis
INPUT
SHIFT
REGISTER
COMP
SAMPLE
AND
HOLD
12-BIT
CAPACITIVE
DAC
OUTPUT
SHIFT
REGISTER
12-BIT
SAR
CONTROL
AND
TIMING
V
CC
8
ANALOG
INPUT MUX
2
3
V
REF
5
GND
4
–IN
+IN
D
OUT
6
1
CLK
7
CS
LTC1292/7 BD
D
OUT
1.4V
3kΩ
100pF
TEST POINT
LTC1292/7 TC03
D
OUT
3k
100pF
TEST POINT
5V t
dis
WAVEFORM 2, t
en
t
dis
WAVEFORM 1
LTC1292/7 TC02
5V
A
A
I
OFF
I
ON
POLARITY
OFF CHANNEL
ON CHANNEL
LTC1292/7 TC01
CLK
D
OUT
0.8V
t
dDO
0.4V
2.4V
LTC1292/7 TC04
D
OUT
0.4V
2.4V
t
r
t
f
LTC1292/7 TC05
D
OUT
WAVEFORM 1
(SEE NOTE 1)
2.0V
t
dis
90%
10%
D
OUT
WAVEFORM 2
(SEE NOTE 2)
CS
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1292/7 TC06