Datasheet
10
LTC1292/LTC1297
12927fb
the MPU. The data is right-justified in the two memory
locations (Figure 2). This was made possible by delaying
the falling edge of CS till after the second CLK. ANDing the
first byte with 0F
HEX
clears the four most significant bits.
This operation was not included in the code. It can be
inserted in the data gathering loop or outside the loop
when the data is processed.
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
LABEL MNEMONIC OPERAND COMMENTS
LDAA #$50 CONFIGURATION DATA FOR SPCR
STAA $1028 LOAD DATA INTO SPCR ($1028)
LDAA #$1B CONFIG. DATA FOR PORT D DDR
STAA $1009 LOAD DATA INTO PORT D DDR
LDAA #$00 LOAD DUMMY DIN WORD INTO
ACC A
STAA $50 LOAD DUMMY DIN DATA INTO $50
LOOP LDX #$1000 LOAD INDEX REGISTER X WITH
$1000
LDAB #$00 LOAD ACC B WITH $00
LDAA $50 LOAD DUMMY DIN INTO ACC A
FROM $50
STAA $102A LOAD DUMMY DIN INTO SPI,
START SCK
NOP DELAY CS FALL TIME TO RIGHT
JUSTIFY DATA
MC68HC11 CODE for LTC1292 Interface
STAB $08, X D0 GOES LOW (CS GOES LOW)
NOP 6 NOPS FOR TIMING
LDAA $1029 CHECK SPI STATUS REG
LDAA $102A LOAD LTC1292 MSBs INTO ACC A
STAA $61 STORE MSBs IN $61
STAA $102A LOAD DUMMY DIN INTO SPI,
START SCK
NOPS 6 NOPS FOR TIMING
BSET $08,X,$01 D0 GOES HIGH (CS GOES HIGH)
LDAA $1029 CHECK SPI STATUS REGISTER
LDAA $102A LOAD LTC1292 LSBs IN ACC
STAA $62 STORE LSBs IN $62
JMP LOOP START NEXT CONVERSION
LABEL MNEMONIC OPERAND COMMENTS
BYTE 2
B3B7
B6
B5
B4 B2
B0
B1
B10 B9 B8B11
OO
OO
BYTE 1
D
OUT
FROM LTC1292 STORED ON MC68HC11 RAM
LOCATION #61
LOCATION #62
MSB
LTC1292/7 F02
CLK
D
OUT
LTC1292
CS
ANALOG
INPUTS
DO
SCK
MISO
MC68HC11
Figure 2. Hardware and Software Interface to Motorola MC68HC11 Microcontroller
Figure 3. Data Exchange Between LTC1297 and MC68HC11
For the LTC1297 (Figure 3) a delay must be introduced to
accommodate the setup time, t
suCS
, before the dummy
D
IN
word is sent to the data register. The first 8-bit transfer
clocks B11 through B6 of the A/D conversion result into
the processor. The second 8-bit transfer clocks the re-
maining bits B5 through B0 into the MPU. Note B1 and B2
from the LSB-first data word have also been clocked in.
CLK
CS
D
OUT
MPU
RECEIVED WORD
LTC1292/7 F03
B7
B6
B5 B4
B3 B2
B1
B0
B1
B8
B9
B10
B11
BYTE 2
B8 B7
B6B9
B10
0
?
B11
1ST TRANSFER
2ND TRANSFER
BYTE 1
B0 B1
B2
B1B2
B4
B5
B3
B2
B3