Datasheet

7
LTC1291
1291fa
TEST CIRCUITS
Voltage Waveforms for D
OUT
Rise and Fall Times, t
r
, t
f
Voltage Waveforms for D
OUT
Delay Time, t
dDO
CLK
D
OUT
0.8V
t
dDO
0.4V
2.4V
1291 TC03
D
OUT
0.4V
2.4V
t
r
t
f
1291 TC04
Voltage Waveforms for t
en
D
OUT
CS
START
0.8V
t
en
B11
1291 TC07
1
2
345
D
IN
CLK
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
being transmitted on the falling CLK edge and captured on
the rising CLK edge in both transmitting and receiving
systems.
The LTC1291 is a data acquisition component which
contains the following functional blocks:
1. 12-bit successive approximation capacitive A/D
converter
2. Analog multiplexer (MUX)
3. Sample-and-hold (S/H)
4. Synchronous, half duplex serial interface
5. Control and timing logic
DIGITAL CONSIDERATIONS
Serial Interface
The LTC1291 communicates with microprocessors and
other external circuitry via a synchronous, half duplex,
4-wire serial interface (see Operating Sequence). The
clock (CLK) synchronizes the data transfer with each bit
Figure 1
The input data is first received and then the A/D conversion
result is transmitted (half duplex). Because of the half
duplex operation D
IN
and D
OUT
may be tied together
allowing transmission over just 3 wires: CS, CLK and
CS
D
OUT
1
D
IN
1
SHIFT MUX
ADDRESS IN
1 NULL
BIT
SHIFT A/D CONVERSION
RESULT OUT
1291 F01
D
IN
2
D
OUT
2