Datasheet

16
LTC1291
1291fa
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
Figure 9. “+” and “–” Input Settling Windows
VERTICAL: 5mV/DIV
HORIZONTAL: 20µs/DIVHORIZONTAL: 500ns/DIV
Figure 10. Adequate Settling of Op Amp Driving Analog Input
D
IN
CLK
START
HI-Z
LTC1291 F09
CS
1ST BIT TEST “–” INPUT MUST
SETTLE DURING THIS TIME
t
SMPL
“+” INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
SGL/
DIFF
MSBF
PS
D
OUT
B11
SAMPLE
HOLD
ODD/
SIGN
Figure 11. Poor Op Amp Settling Can Cause A/D Errors
(Note Horizontal Scale)
VERTICAL: 5mV/DIV