Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - ADC 12 Bit PDIP 8

LTC1291

1291fa

The LTC

1291 is a data acquisition system that contains

a serial I/O successive approximation A/D converter. It

uses LTCMOS

switched capacitor technology to per-

form a 12-bit unipolar A/D conversion. The input multi-

plexer can be configured for either single-ended or differ-

ential inputs. An on-chip sample-and-hold is included on

the “+” input. When the LTC1291 is idle, it can be powered

down in applications where low power consumption is

desired. An external reference is not required because the

LTC1291 takes its reference from the power supply (V

All these features are packaged in an 8-pin DIP.

The serial I/O is designed to communicate without external

hardware to most MPU serial ports and all MPU parallel

I/O ports allowing data to be transmitted over three or four

wires. Given the accuracy, ease of use and small package

size, this device is well suited for digitizing analog signals

in remote applications where minimum number of inter-

connects, small physical size, and low power consump-

tion are important.

LTCMOS

is a trademark of Linear Technology Corporation

, LTC and LT are registered trademarks of Linear Technology Corporation.

FEATURES

DESCRIPTIO

KEY SPECIFICATIO S

TYPICAL APPLICATIO

Single Chip 12-Bit

Data Acquisition System

■

Built-In Sample-and-Hold

■

Single Supply 5V Operation

■

Power Shutdown

■

Direct 3- or 4-Wire Interface to Most MPU Serial

Ports and All MPU Parallel Ports

■

Two-Channel Analog Multiplexer

■

Analog Inputs Common Mode to Supply Rails

■

8-Pin DIP Package

■

Resolution: 12 Bits

■

Fast Conversion Time: 12µs Max Over Temp.

■

Low Supply Current:

6.0mA (Typ) Active Mode

10µA (Max) Shutdown Mode

CH0

GND

OUT

CLK

REF

)

LTC1291

2-CHANNEL

MUX*

CH1

0.1µF

22µF

TANTALUM

*FOR OVERVOLTAGE PROTECTION, LIMIT THE INPUT CURRENT TO 15mA

PER PIN OR CLAMP THE INPUTS TO V

AND GND WITH 1N4148 DIODES.

CONVERSION RESULTS ARE NOT VALID WHEN THE SELECTED CHANNEL OR

THE OTHER CHANNEL IS OVERVOLTAGED (V

< GND OR V

> V

). SEE

SECTION ON OVERVOLTAGE PROTECTION IN THE APPLICATIONS INFORMATION.

1291 TA01

MC68HC11

SCK

MISO

MOSI

CODE

–0.5

DELTA (LSB)

–0.4

–0.2

–0.1

0.5

0.2

1024

2048

2560

1291 TA02

–0.3

0.3

0.4

0.1

512 1536

3072

3584

4096

Channel-to-Channel

INL Matching

2-Channel 12-Bit Data Acquisition System

Summary of content (20 pages)

PAGE 1
LTC1291 Single Chip 12-Bit Data Acquisition System U FEATURES ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Built-In Sample-and-Hold Single Supply 5V Operation Power Shutdown Direct 3- or 4-Wire Interface to Most MPU Serial Ports and All MPU Parallel Ports Two-Channel Analog Multiplexer Analog Inputs Common Mode to Supply Rails 8-Pin DIP Package U KEY SPECIFICATIO S ■ ■ ■ Resolution: 12 Bits Fast Conversion Time: 12µs Max Over Temp. Low Supply Current: 6.
PAGE 2
LTC1291 U U W W W AXI U RATI GS W (Notes 1 and 2) U ABSOLUTE PACKAGE/ORDER I FOR ATIO Supply Voltage (VCC) to GND .................................. 12V Voltage Analog Inputs ............................ –0.3V to VCC + 0.3V Digital Inputs ........................................ –0.3V to 12V Digital Outputs .......................... –0.3V to VCC + 0.3V Power Dissipation ............................................. 500mW Operating Temperature Range LTC1291BC, LTC1291CC, LTC1291DC ..............
PAGE 3
LTC1291 AC CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 4
LTC1291 U W TYPICAL PERFOR A CE CHARACTERISTICS Change in Offset vs Supply Voltage 10 10 CLK = 1MHz TA = 25°C CLK = 1MHz VCC = 5V 9 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 8 6 4 8 7 6 5 2 4 5 4 3 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE (°C) 6 SUPPLY VOLTAGE (V) 1291 G01 0.4 0.3 0.2 0.1 0 4.0 4.5 5.5 5.0 SUPPLY VOLTAGE (V) 6.0 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 4.0 Change in Gain Error vs Supply Voltage 4.5 5.5 5.
PAGE 5
LTC1291 U W TYPICAL PERFOR A CE CHARACTERISTICS 1.0 250 MAXIMUM CLK FREQUENCY* (MHz) LSB-FIRST DATA 100 50 0 –50 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 0.8 +VIN 0.6 RSOURCE– – –IN 0.
PAGE 6
LTC1291 W BLOCK DIAGRA 7 VCC (VREF) DIN CH0 CH1 8 INPUT SHIFT REGISTER 5 2 3 ANALOG INPUT MUX OUTPUT SHIFT REGISTER SAMPLE AND HOLD CLK 6 DOUT COMP 12-BIT SAR 12-BIT CAPACITIVE DAC CONTROL AND TIMING 4 GND 1 CS 1291 BD TEST CIRCUITS Load Circuit for tdis and ten Load Circuit for tdDO, tr and tf 1.4V TEST POINT 3k 3k DOUT TEST POINT 5V tdis WAVEFORM 2, ten DOUT 100pF 100pF tdis WAVEFORM 1 1291 TC02 1291 TC05 On and Off Channel Leakage Current Voltage Waveforms for tdis 2.
PAGE 7
LTC1291 TEST CIRCUITS Voltage Waveforms for DOUT Delay Time, tdDO Voltage Waveforms for DOUT Rise and Fall Times, tr, tf CLK 2.4V DOUT 0.8V tdDO 0.4V 2.4V tr tf DOUT 1291 TC04 0.4V 1291 TC03 Voltage Waveforms for ten CS DIN START CLK 2 1 3 4 5 DOUT B11 0.8V ten U W U UO APPLICATI 1291 TC07 S I FOR ATIO The LTC1291 is a data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive A/D converter 2.
PAGE 8
LTC1291 U W U UO APPLICATI S I FOR ATIO the conversion appears MSB-first on the DOUT line. The conversion result is output, bit by bit, as the conversion is performed. At the end of the data exchange, CS should be brought high. This resets the LTC1291 in preparation for the next data exchange. DATA (DIN/DOUT). Data transfer is initiated by a falling chip select (CS) signal. After CS falls, the LTC1291 looks for a start bit.
PAGE 9
LTC1291 W U U UO APPLICATI S I FOR ATIO Input Data Word The 4-bit data word is clocked into the DIN pin on the rising edge of the clock after chip select goes low and the start bit has been recognized. Further inputs on the DIN pin are then ignored until the next CS cycle.
PAGE 10
LTC1291 W U U UO APPLICATI S I FOR ATIO Output Code The LTC1291 performs a unipolar conversion. The following shows the output code and transfer curve: Unipolar Transfer Curve Unipolar Output Code 111111111111 • • • 000000000001 000000000000 1291 AI05a Microprocessor Interfaces The LTC1291 can interface directly (without external hardware) to most popular microprocessors’s (MPU) synchronous serial formats (see Table 1).
PAGE 11
LTC1291 W U U UO APPLICATI S I FOR ATIO Timing Diagram for Interface to the MC68HC11 CS CLK SGL/ START DIFF DIN ODD/ EVEN MSBF DON'T CARE PS DOUT MPU TRANSMIT WORD 0 0 0 0 0 0 1 ODD/ EVEN MSBF SGL/ DIFF PS ? ? ? B9 B8 X X X X B7 X B6 B5 B4 B3 B2 B1 B0 X X X X X X X B2 B1 B0 BYTE 2 ? ? B10 X BYTE 1 MPU RECEIVED WORD B11 ? ? ? ? ? 0 ? B11 BYTE 3 (DUMMY) B10 B8 B9 B7 B6 B5 BYTE 2 BYTE 1 B4 B3 BYTE 3 LTC1291 AI06 Hardware and Soft
PAGE 12
LTC1291 W U UO LABEL MNEMONIC LDAA WAIT1 BPL LDAA STAA WAIT2 LDAA BPL LDAA STAA LDAA U APPLICATI S I FOR ATIO OPERAND $1029 WAIT1 $51 $102A $1029 WAIT2 $102A $62 $52 COMMENTS CHECK SPI STATUS REG CHECK IF TRANSFER IS DONE LOAD DIN INTO ACC A FROM $51 LOAD DIN INTO SPI, START SCK CHECK SPI STATUS REG CHECK IF TRANSFER IS DONE LOAD LTC1291 MSBs INTO ACC A STORE MSBs IN $62 LOAD DUMMY DIN INTO ACC A FROM $52 Interfacing to the Parallel Port of the Intel 8051 Family The Intel 8051 has been chosen to sh
PAGE 13
LTC1291 W U U UO APPLICATI S I FOR ATIO 8051 Code In this example the input MUX is configured to accept a differential input between CH0 and CH1. The result from the conversion is clocked out MSB-first. LABEL MNEMONIC SETB CONT MOV CLR MOV LOOP1 RLC CLR MOV SETB DJNZ MOV CLR MOV LOOP MOV RLC SETB CLR DJNZ MOV MOV SETB OPERAND P1.4 A,#98H P1.4 R4,#05H A P1.3 P1.2,C P1.3 R4,LOOP1 P1,#04H P1.3 R4,#09H C,P1.2 A P1.3 P1.3 R4,LOOP R2,A C,P1.2 P1.
PAGE 14
LTC1291 U W U UO APPLICATI S I FOR ATIO Grounding The LTC1291 should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, use a PC board. The ground pin (Pin 4) should be tied directly to the ground plane with minimum lead length. Figure 4 shows an example of an ideal LTC1291 ground plane for a two-sided board.
PAGE 15
LTC1291 W U U UO APPLICATI S I FOR ATIO or GND lead will cause gain errors and offset errors (Figure 7). For the best performance the LTC1291 should be soldered directly to the PC board. If the source can not be placed next to the pin and the gain parameter is important, the pin should be Kelvin-sensed to eliminate parasitic resistances due to long PC traces. For example, 0.1Ω of resistance in the VCC lead can typically cause 0.5LSB (ICC • 0.1Ω/ VCC) of gain error for VCC = 5V.
PAGE 16
LTC1291 U W U UO APPLICATI S I FOR ATIO HOLD SAMPLE CS CLK DIN SGL/ DIFF START ODD/ SIGN MSBF PS tSMPL “+” INPUT MUST SETTLE DURING THIS TIME DOUT B11 HI-Z 1ST BIT TEST “–” INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT LTC1291 F09 VERTICAL: 5mV/DIV VERTICAL: 5mV/DIV Figure 9. “+” and “–” Input Settling Windows HORIZONTAL: 500ns/DIV Figure 10. Adequate Settling of Op Amp Driving Analog Input HORIZONTAL: 20µs/DIV Figure 11.
PAGE 17
LTC1291 U W U UO APPLICATI S I FOR ATIO RC Input Filtering It is possible to filter the inputs with an RC network as shown in Figure 12. For large values of CF (e.g., 1µF) the capacitive input switching currents are averaged into a net DC current. A filter should be chosen with a small resistor and a large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = 100pF • VIN/tCYC and is roughly proportional to VIN.
PAGE 18
LTC1291 U W U UO APPLICATI S I FOR ATIO Overvoltage Protection Applying signals to the LTC1291’s analog inputs that exceed the positive supply or that go below ground will degrade the accuracy of the A/D and possibly damage the device. For example, this condition will occur if a signal is applied to the analog inputs before power is applied to the LTC1291. It can also happen if the input source is operating from supplies of larger value than the LTC1291 supply.
PAGE 19
LTC1291 W U U UO APPLICATI S I FOR ATIO A “Quick Look” Circuit for the LTC1291 Users can get a quick look at the function and timing of the LTC1291 by using the following simple circuit (Figure 16). DIN is tied to VCC. This requires VIN be applied to CH1 with respect to the ground plane. The data is output MSB-first. CS is driven at 1/64, the clock frequency by the 74HC393 and DOUT outputs the data.
PAGE 20
LTC1291 U PACKAGE DESCRIPTIO J8 Package 8-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) .023 – .045 (0.584 – 1.143) HALF LEAD OPTION .045 – .068 (1.143 – 1.650) FULL LEAD OPTION .200 (5.080) MAX .300 BSC (7.62 BSC) CORNER LEADS OPTION (4 PLCS) .015 – .060 (0.381 – 1.524) .008 – .018 (0.203 – 0.457) .405 (10.287) MAX .005 (0.127) MIN 8 7 6 5 .025 (0.635) RAD TYP .220 – .310 (5.588 – 7.