Datasheet

4
LTC1290
1290fe
AC CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. (Note 3)
LTC1290B/LTC1290C/LTC1290D
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SCLK
Shift Clock Frequency V
CC
= 5V (Note 6) 0 2.0 MHz
f
ACLK
A/D Clock Frequency V
CC
= 5V (Note 6) (Note 10) 4.0 MHz
t
ACC
Delay Time from CS↓ to D
OUT
Data Valid (Note 9) 2 ACLK
Cycles
t
SMPL
Analog Input Sample Time See Operating Sequence 7 SCLK
Cycles
t
CONV
Conversion Time See Operating Sequence 52 ACLK
Cycles
t
CYC
Total Cycle Time See Operating Sequence (Note 6) 12 SCLK + Cycles
56 ACLK
t
dDO
Delay Time, SCLK↓ to D
OUT
Data Valid See Test Circuits LTC1290BC, LTC1290CC ● 130 220 ns
LTC1290DC, LTC1290BI
LTC1290CI, LTC1290DI
LTC1290BM, LTC1290CM ● 180 270 ns
LTC1290DM
(OBSOLETE)
t
dis
Delay Time, CS↑ to D
OUT
Hi-Z See Test Circuits ● 70 100 ns
t
en
Delay Time, 2nd ACLK↓ to D
OUT
Enabled See Test Circuits ● 130 200 ns
t
hCS
Hold Time, CS After Last SCLK↓ V
CC
= 5V (Note 6) 0 ns
t
hDI
Hold Time, D
IN
After SCLK↑ V
CC
= 5V (Note 6) 50 ns
t
hDO
Time Output Data Remains Valid After SCLK↓ 50 ns
t
f
D
OUT
Fall Time See Test Circuits ● 65 130 ns
t
r
D
OUT
Rise Time See Test Circuits ● 25 50 ns
t
suDI
Setup Time, D
IN
Stable Before SCLK↑ V
CC
= 5V (Note 6) 50 ns
t
suCS
Setup Time, CS↓ Before Clocking in (Notes 6, 9) 2 ACLK Cycles
First Address Bit + 100ns
t
WHCS
CS High Time During Conversion V
CC
= 5V (Note 6) 52 ACLK
Cycles
C
IN
Input Capacitance Analog Inputs On Channel 100 pF
Analog Inputs Off Channel 5 pF
Digital Inputs 5 pF