Datasheet

17
LTC1290
1290fe
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
Hardware and Software Interface to Motorola
MC68HC05C4 Processor
LTC1290 • AI09
SCLK
D
OUT
LTC1290
CS
ANALOG
INPUTS
CO
SCK
MISO
MC68HC05C4
D
IN
MOSI
BYTE 1
B10 B9 B8B11 B6 B5 B4B7
D
OUT
from LTC1290 Stored in MC68HC05C4 RAM
MSB*
LOCATION $61
BYTE 2
B2 B1 B0B3 0 0 00
LSB
LOCATION $62
•
•
•
•
*B11 IS MSB IN UNIPOLAR OR SIGN BIT IN BIPOLAR
MC68HC05C4 Code
MNEMONIC COMMENTS
LDA #$50 Configuration Data for SPCR
STA $0A Load Data Into SPCR ($0A)
LDA #$FF Config. Data for Port C DDR
STA $06 Load Data Into Port C DDR
LDA #$0F Load LTC1290 D
IN
Data Into ACC
STA $50 Load LTC1290 D
IN
Data Into $50
START BCLR 0,$20 CO Goes Low (CS Goes Low)
LDA $50 Load D
IN
Into ACC from $50
STA $0C Load D
IN
Into SPI, Start SCK
NOP 8 NOPs for Timing
LDA $0B Check SPI Status Reg
LDA $0C Load LTC1290 MSBs Into ACC
STA $61 Store MSBs in $61
STA $0C Start Next SPI Cycle
NOP 6 NOPs for Timing
BSET 0,$02 CO Goes High (CS Goes High)
LDA $0B Check SPI Status Register
LDA $0C Load LTC1290 LSBs Into ACC
STA $62 Store LSBs in $62
Parallel Port Microprocessors
When interfacing the LTC1290 to an MPU which has a
parallel port, the serial signals are created on the port with
software. Three MPU port lines are programmed to create
the CS, SCLK and D
IN
signals for the LTC1290. A fourth
port line reads the D
OUT
line. An example is made of the
Intel 8051/8052/80C252 family.
Intel 8051
To interface to the 8051, the LTC1290 is programmed for
MSB-first format and 12-bit word length. The 8051 gener-
ates CS, SCLK and D
IN
on three port lines and reads D
OUT
on the fourth.
Hardware and Software Interface to Intel 8051 Processor
LTC1290 • AI10
D
IN
CS
ACLK
LTC1290
D
OUT
ANALOG
INPUTS
P1.1
P1.2
P1.4
ALE
8051
SCLK
P1.3
B10 B9 B8B11 B6 B5 54B7
D
OUT
from LTC1290 Stored in 8051 RAM
MSB*
R2
B2 B1 B0B3 0 0 00
LSB
R3
•
•
•
•
•
•
•
•
*B11 IS MSB IN UNIPOLAR OR SIGN BIT IN BIPOLAR