Datasheet
10
LTC1290
1290fe
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
previous conversion is output on the D
OUT
line. At the end
of the data exchange the requested conversion begins and
CS should be brought high. After t
CONV
, the conversion is
complete and the results will be available on the next data
transfer cycle. As shown below, the result of a conversion
is delayed by one CS cycle from the input word requesting it.
The LTC1290 is a data acquisition component which
contains the following functional blocks:
1. 12-bit successive approximation capacitive A/D
converter
2. Analog multiplexer (MUX)
3. Sample-and-hold (S/H)
4. Synchronous, full duplex serial interface
5. Control and timing logic
DIGITAL CONSIDERATIONS
Serial Interface
The LTC1290 communicates with microprocessors and
other external circuitry via a synchronous, full duplex,
four-wire serial interface (see Operating Sequence). The
shift clock (SCLK) synchronizes the data transfer with
each bit being transmitted on the falling SCLK edge and
captured on the rising SCLK edge in both transmitting and
receiving systems. The data is transmitted and received
simultaneously (full duplex).
Data transfer is initiated by a falling chip select (CS) signal.
After the falling CS is recognized, an 8-bit input word is
shifted into the D
IN
input which configures the LTC1290
for the next conversion. Simultaneously, the result of the
SGL/
DIFF
SELECT
1
SELECT
0
UNI MSBF WL1
MUX ADDRESS
MSB-FIRST/
LSB-FIRST
UNIPOLAR/
BIPOLAR
WORD
LENGTH
LTC1290 • AI02
ODD/
SIGN
WL0
D
IN
D
OUT
D
OUT
WORD 0
D
IN
WORD 1
DATA
TRANSFER
D
OUT
WORD 2
D
IN
WORD 3
D
OUT
WORD 1
D
IN
WORD 2
DATA
TRANSFER
t
CONV
A/D
CONVERSION
t
CONV
A/D
CONVERSION
LTC1290 • AI01
Input Data Word
The LTC1290 8-bit data word is clocked into the D
IN
input
on the first eight rising SCLK edges after chip select is
recognized. Further inputs on the D
IN
pin are then ignored
until the next CS cycle. The eight bits of the input word are
defined as follows:
123456789101112
t
CONV
t
CYC
SHIFT CONFIGURATION
WORD IN
t
SMPL
SHIFT A/D RESULT OUT AND
NEW CONFIGURATION WORD IN
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
(SB)
LTC1290 • AI03
SCLK
D
IN
D
OUT
CS
DON’T CARE
DON’T CARE
Operating Sequence
(Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length)