LTC1290 Single Chip 12-Bit Data Acquisition System U FEATURES DESCRIPTIO ■ The LTC®1290 is a data acquisition component which contains a serial I/O successive approximation A/D converter. It uses LTCMOSTM switched capacitor technology to perform either 12-bit unipolar or 11-bit plus sign bipolar A/D conversions. The 8-channel input multiplexer can be configured for either single-ended or differential inputs (or combinations thereof).
LTC1290 W W W AXI U U ABSOLUTE RATI GS (Notes 1, 2) – Supply Voltage (VCC) to GND or V ........................ 12V Operating Temperature Range – Negative Supply Voltage (V ) .................... – 6V to GND LTC1290BC, LTC1290CC, LTC1290DC .... Voltage Analog/Reference Inputs ......... (V –) – 0.3V to VCC + 0.3V Digital Inputs ........................................ – 0.3V to 12V Digital Outputs ........................... – 0.3V to VCC + 0.3V Power Dissipation ......................................
LTC1290 U U W CO VERTER A D ULTIPLEXER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) LTC1290D TYP MAX UNITS ±1.5 ±1.5 LSB ±0.5 ±0.5 ±0.75 LSB ● ±0.5 ±1.0 ±4.0 LSB ● 12 12 12 Bits CONDITIONS Offset Error (Note 4) ● ±1.
LTC1290 AC CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
LTC1290 U DIGITAL A D DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) LTC1290B/LTC1290C/LTC1290D MIN TYP MAX SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VCC = 5.25V ● VIL Low Level Input Voltage VCC = 4.75V ● IIH High Level Input Current VIN = VCC IIL Low Level Input Current VIN = 0V VOH High Level Output Voltage VCC = 4.75V 2.0 UNITS V 0.8 V ● 2.
LTC1290 U W TYPICAL PERFOR A CE CHARACTERISTICS 18 14 10 6 8 7 6 5 4 6 8 SUPPLY VOLTAGE, VCC (V) 10 CHANGE IN GAIN ERROR (LSB = 1 • VREF) 4096 1.25 VCC = 5V LINEARITY ERROR (LSB = 1 • VREF) 4096 0.5 1.00 0.75 0.50 0.25 0.3 5 –0.2 –0.3 –0.4 VCC = 5V 1 3 2 4 REFERENCE VOLTAGE, VREF (V) 5 0.4 0.2 0.1 0 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE, TA (°C) 1290 • TPC07 MAGNITUDE OF GAIN CHANGE ⏐∆GAIN⏐ (LSB) 0.3 ACLK = 4MHz VCC = 5V VREF = 5V 0.3 0.2 0.
LTC1290 U W TYPICAL PERFOR A CE CHARACTERISTICS Maximum Filter Resistor vs Cycle Time Sample-and-Hold Acquisition Time vs Source Resistance 100 1k 100 RFILTER + VIN CFILTER ≥ 1µF 10 – 1.0 10 1000 100 VIN 10 RSOURCE+ + 1k 140 120 100 80 60 40 20 0 3.00 1.00 2.00 ACLK FREQUENCY (MHz) 4.00 4 3 2 1290 • TPC12 Noise Error vs Reference Voltage 2.
LTC1290 U U U PI FU CTIO S DIN (Pin 17): Digital Data Input. The A/D configuration word is shifted into this input after CS is recognized. ACLK (Pin 19): A/D Conversion Clock. This clock controls the A/D conversion process. SCLK (Pin 18): Shift Clock. This clock synchronizes the serial data transfer. VCC (Pin 20): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
LTC1290 TEST CIRCUITS Voltage Waveforms for DOUT Delay Time, tdDO SCLK 0.8V tdDO 2.4V DOUT 0.4V LTC1290 • TC03 Voltage Waveform for DOUT Rise and Fall Times, tr, tf 2.4V DOUT 0.4V tr tf LTC1290 • TC04 Load Circuit for tdDO, tr and tf 1.4V 3k DOUT TEST POINT 100pF 1290 • TC05 Voltage Waveforms for ten and tdis 1 2 ACLK 2.0V CS DOUT WAVEFORM 1 (SEE NOTE 1) 2.4V ten DOUT WAVEFORM 2 (SEE NOTE 2) 90% tdis 0.
LTC1290 W U U UO APPLICATI S I FOR ATIO The LTC1290 is a data acquisition component which contains the following functional blocks: previous conversion is output on the DOUT line. At the end of the data exchange the requested conversion begins and CS should be brought high. After tCONV, the conversion is complete and the results will be available on the next data transfer cycle. As shown below, the result of a conversion is delayed by one CS cycle from the input word requesting it. 1.
LTC1290 W U U UO APPLICATI S I FOR ATIO MUX Address The first four bits of the input word assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the + and – signs in the selected row of Table 1. Note that in differential mode (SGL/DIFF = 0) measurements are limited to four adjacent input pairs with either polarity. In single-ended mode, all input channels are measured with respect to COM.
LTC1290 W U U UO APPLICATI S I FOR ATIO Unipolar/Bipolar (UNI) The fifth input bit (UNI) determines whether the conversion will be unipolar or bipolar. When UNI is a logical one, a unipolar conversion will be performed on the selected input voltage. When UNI is a logical zero, a bipolar conversion will result. The input span and code assignment for each conversion type are shown in the figures below.
LTC1290 U W U UO APPLICATI S I FOR ATIO MSB-First/LSB-First Format (MSBF) The output data of the LTC1290 is programmed for MSBfirst or LSB-first sequence using the MSBF bit. For MSB first output data the input word clocked to the LTC1290 should always contain a logical one in the sixth bit location (MSBF bit). Likewise for LSB-first output data the input word clocked to the LTC1290 should always contain a zero in the MSBF bit location. The MSBF bit affects only the order of the output data word.
LTC1290 W U U UO APPLICATI S I FOR ATIO 8-Bit Word Length tSMPL tCONV CS SCLK 1 8 (SB) DOUT MSB-FIRST B11 B10 B9 B8 B7 B6 B5 B4 DOUT LSB-FIRST B0 B1 B2 B3 B4 B5 B6 B7 THE LAST FOUR BITS ARE TRUNCATED 12-Bit Word Length tSMPL tCONV CS 1 SCLK 10 12 (SB) DOUT MSB-FIRST B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 DOUT LSB-FIRST B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B0 (SB) B11 16-Bit Word Length tSMPL tCONV CS SCLK 1 12 16 (SB) DOUT MSB-FIRST B11 B10
LTC1290 W U U UO APPLICATI S I FOR ATIO SHIFT MUX ADDRESS IN tSMPL SAMPLE ANALOG INPUT 48 TO 52 ACLK CYC SHIFT RESULT OUT AND NEW ADDRESS IN CS SCLK DON’T CARE DIN DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 LTC1290 F03 Figure 3.
LTC1290 W U U UO APPLICATI S I FOR ATIO Table 2. Microprocessors with Hardware Serial Interfaces Compatible with the LTC1290** PART NUMBER TYPE OF INTERFACE Motorola MC6805S2, S3 MC68HC11 MC68HC05 SPI SPI SPI CDP68HC05 SPI RCA National MICROWIRE (COP402) The COP402 transfers data MSB first and in 4-bit increments (nibbles). This is easily accommodated by setting the LTC1290 to MSB-first format and 12-bit word length. The data output word is then received by the COP402 in three 4-bit blocks.
LTC1290 W U U UO APPLICATI S I FOR ATIO Hardware and Software Interface to Motorola MC68HC05C4 Processor CO CS • • • • When interfacing the LTC1290 to an MPU which has a parallel port, the serial signals are created on the port with software. Three MPU port lines are programmed to create the CS, SCLK and DIN signals for the LTC1290. A fourth port line reads the DOUT line. An example is made of the Intel 8051/8052/80C252 family.
LTC1290 W U U UO APPLICATI S I FOR ATIO 8051 Code Sharing the Serial Interface MNEMONIC CONT LOOP DELAY MOV CLR SETB MOV CLR MOV NOP MOV RLC MOV SETB CLR DJNZ MOV MOV CLR RLC SETB CLR MOV RLC SETB CLR MOV RLC SETB CLR MOV RRC RRC RRC RRC MOV SETB CLR SETB P1,#02H P1.3 P1.4 A,#0EH P1.4 R4,#08H C,P1.1 A P1.2,C P1.3 P1.3 R4,LOOP R2,A C,P1.1 A A P1.3 P1.3 C,P1.1 A P1.3 P1.3 C,P1.1 A P1.3 P1.3 C, P1.1 A A A A R3,A P1.3 P1.3 P1.
LTC1290 W U U UO APPLICATI S I FOR ATIO VCC 1 VERTICAL: 0.5mV/DIV 22µF TANTALUM 20 HORIZONTAL: 10µs/DIV Figure 7. Poor VCC Bypassing. Noise and Ripple Can Cause A/D Errors V– 10 ANALOG GROUND PLANE 0.1µF CERAMIC DISK CS Figure 6. Example Ground Plane for the LTC1290 Figure 6 shows an example of an ideal ground plane design for a two-sided board. Of course, this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. VERTICAL: 0.
LTC1290 W U U UO APPLICATI S I FOR ATIO “–” Input Settling “+” INPUT RSOURCE + LTC1290 VIN + RSOURCE – C1 4TH SCLK RON = 500Ω “–” INPUT LAST SCLK CIN = 100pF VIN – C2 LTC1290 F09 Figure 9. Analog Input Equivalent Circuit “+” Input Settling This input capacitor is switched onto the “+” input during the sample phase (tSMPL, see Figure 10).
LTC1290 U W U UO APPLICATI S I FOR ATIO maximum clock rates (ACLK = 4MHz and SCLK = 2MHz). Figures 11 and 12 show examples of adequate and poor op amp settling. RFILTER IDC VIN "+" CFILTER LTC1290 "–" LTC1290 F13 VERTICAL: 5mV/DIV Figure 13. RC Input Filtering Input Leakage Current HORIZONTAL: 500ns/DIV Figure 11. Adequate Settling of Op Amps Driving Analog Input Input leakage currents can also create errors if the source resistance gets too large.
LTC1290 W U U UO S I FOR ATIO With differential inputs or when the COM pin is not tied to ground, the A/D no longer converts just a single voltage but rather the difference between two voltages. In these cases, the voltage on the selected “+” input is still sampled and held and therefore may be rapidly time varying just as in singleended mode. However, the voltage on the selected “–” input must remain constant and be free of noise and ripple throughout the conversion time.
LTC1290 U W U UO APPLICATI S I FOR ATIO 6. Reduced Reference Operation The effective resolution of the LTC1290 can be increased by reducing the input span of the converter. The LTC1290 exhibits good linearity and gain over a wide range of reference voltages (see the typical curves of Linearity and Gain Error vs Reference Voltage). However, care must be taken when operating at low values of VREF because of the reduced LSB step size and the resulting higher accuracy requirement placed on the converter.
LTC1290 U UO S I FOR ATIO fIN = 1kHz fSAMPLE = 50.6kHz SNR = 73.25dB 0 –20 MAGNITUDE (dB) W U APPLICATI –20 MAGNITUDE (dB) –40 –60 –80 –40 –60 –80 –100 –100 –120 –120 –140 0 4 8 12 16 20 FREQUENCY (kHz) fIN = 25kHz fSAMPLE = 50.6kHz SNR = 72.54dB 0 –140 24 0 4 8 12 16 20 FREQUENCY (kHz) 1290 • F17a 1290 • F17b Figure 17a. LTC1290 FFT Plot fIN1 = 5.1kHz fIN2 = 5.6kHz fSAMPLE = 50.6kHz 0 11.6 –20 11.2 MAGNITUDE (dB) EFFECTIVE NUMBER OF BITS Figure 17b.
LTC1290 W U UO VIN U APPLICATI S I FOR ATIO 1k 5V VCC CH0 22µF LTC1290 DGND V– –5V AGND 0.1µF 1290 F20 Figure 20. Overvoltage Protection for MUX How the various power supplies to the LTC1290 are applied can also lead to overvoltage conditions. For single supply operation (i.e., unipolar mode), if VCC and REF + are not tied together, then VCC should be turned on first, then REF +. If this sequence cannot be met, connecting a diode from REF + to VCC is recommended (see Figure 21).
LTC1290 UO TYPICAL APPLICATI S A “Quick Look” Circuit for the LTC1290 A “Quick Look” Circuit for the LTC1290 Users can get a quick look at the function and timing of the LTC1290 by using the following simple circuit. REF + and DIN are tied to VCC selecting a 5V input span, CH7 as a single-ended input, unipolar mode, MSB-first format and 16-bit word length. ACLK and SCLK are tied together and driven by an external clock. CS is driven at 1/128 the clock rate by the CD4520 and DOUT outputs the data.
LTC1290 UO TYPICAL APPLICATI S SNEAK-A-BITTM The LTC1290’s unique ability to software select the polarity of the differential inputs and the output word length is used to achieve one more bit of resolution. Using the circuit below with two conversions and some software, a 2’s complement 12-bit + sign word is returned to memory inside the MPU. The MC68HC05C4 was chosen as an example, however, any processor could be used.
LTC1290 UO TYPICAL APPLICATI S SNEAK-A-BIT Code SNEAK-A-BIT Code for the LTC1290 Using the MC68HC05C4 DOUT from LTC1290 in MC68HC05C4 RAM MNEMONIC Sign READ –/+: LOCATION $77 B12 B11 B10 B9 LOCATION $87 B4 B3 B2 B1 B8 B7 B6 B5 LSB B0 Filled with 0s DIN Words for LTC1290 MSBF MUX Addr.
LTC1290 UO TYPICAL APPLICATI S Power Shutdown For battery-powered applications it is desirable to keep power dissipation at a minimum. The LTC1290 can be powered down when not in use reducing the supply current from a nominal value of 5mA to typically 5µA (with ACLK turned off). See the curve for Supply Current (Power Shutdown) vs ACLK if ACLK cannot be turned off when the LTC1290 is powered down.
LTC1290 U PACKAGE DESCRIPTIO J Package 20-Lead CERDIP (Narrow 0.300, Hermetic) (LTC DWG # 05-08-1110) 0.300 BSC (0.762 BSC) CORNER LEADS OPTION (4 PLCS) 0.008 – 0.018 (0.203 – 0.457) 0° – 15° 0.200 (5.080) MAX 0.015 – 0.060 (0.381 – 1.524) 0.023 – 0.045 (0.584 – 1.143) HALF LEAD OPTION 0.045 – 0.068 (1.143 – 1.727) FULL LEAD OPTION NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS 1.060 (26.924) MAX 20 19 18 17 16 15 14 13 12 11 2 3 4 5 6 7 8 9 10 0.220 – 0.
LTC1290 U PACKAGE DESCRIPTIO SW Package 20-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620) .050 BSC .045 ±.005 .030 ±.005 TYP .496 – .512 (12.598 – 13.005) NOTE 4 N 20 18 17 16 15 14 13 12 11 N .325 ±.005 .420 MIN 19 .394 – .419 (10.007 – 10.643) NOTE 3 1 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT .005 (0.127) RAD MIN .009 – .013 (0.229 – 0.330) NOTE: 1. DIMENSIONS IN .291 – .299 (7.391 – 7.595) NOTE 4 .010 – .029 × 45° (0.254 – 0.
LTC1290 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1286/LTC1298 12-Bit, Micropower Serial ADC in SO-8 1- or 2-Channel, Autoshutdown LTC1293/LTC1294/LTC1296 12-Bit, Multiplexed Serial ADC 6-, 8- or 8-Channel with Shutdown Output LTC1594/LTC1598 12-Bit, Micropower Serial ADC 4- or 8-Channel, 3V Versions Available 1290fe 32 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.
