Datasheet

9
LTC1273
LTC1275/LTC1276
127356fa
PI
U
FU
U
C
U
S
O
TI
V
SS
(Pin 23): Negative Supply. –5V for LTC1275/
LTC1276. Bypass to AGND with 0.1µF ceramic.
NC (Pin 23): No Connection for LTC1273.
V
DD
(Pin 24): Positive Supply, 5V. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic).
Table 1. Data Bus Output, CS and RD = LOW
Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16
MNEMONIC* D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8
HBEN = LOW DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
HBEN = HIGH DB11 DB10 DB9 DB8 LOW LOW LOW LOW DB11 DB10 DB9 DB8
*D11...D0/8 are the ADC data output pins.
DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
FU TIO AL BLOCK DIAGRA
UU W
C
SAMPLE
CONTROL
LOGIC
INTERNAL
CLOCK
SUCCESSIVE
APPROXIMATION
REGISTER
12
12
OUTPUT
LATCHES
•
•
•
D11
D0/8
BUSY
2.42V
REFERENCE
V
REF(OUT)
DGNDAGND
A
IN
SAMPLE
HOLD
SAMPLE
V
SS
(NC ON LTC1273)V
DD
HBEN
CS
RD
LTC1273/75/76 • FBD
12-BIT
CAPACITIVE
DAC
COMPARATOR
–
+
TEST CIRCUITS
Load Circuits for Access Time
Load Circuits for Output Float Delay
3k
C
L
DBN
DGND
A) HIGH-Z TO V
OH
(t
3
)
AND V
OL
TO V
OH
(t
6
)
C
L
DBN
3k
5V
B) HIGH-Z TO V
OL
(t
3
)
AND V
OH
TO V
OL
(t
6
)
DGND
1273/75/76 • TA07
3k
10pF
DBN
DGND
A) V
OH
TO HIGH-Z
10pF
DBN
3k
5V
B) V
OL
TO HIGH-Z
DGND
1273/75/76 • TA08