Datasheet

9
LTC1274/LTC1277
BLOCK DIAGRA S
W
LTC1274
12-BIT CAPACITIVE DAC
COMPARATOR
C
SAMPLE
•
•
•
D11
D0
BUSY
CONTROL LOGIC
CSCONVST RD
INTERNAL
CLOCK
SLEEP
ZEROING SWITCHES
V
SS
(0V FOR UNIPOLAR MODE OR
–5V FOR BIPOLAR MODE)
V
DD
A
IN
V
REF
REFRDY
AGND
DGND
12
LTC1274 • BD
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT LATCHES
2.42V REF
LTC1277
12-BIT CAPACITIVE DAC
COMPARATOR
C
SAMPLE
•
•
•
•
•
D7
D1/9
D0/8
BUSY V
LOGIC
3V OR 5V
CONTROL LOGIC
CSCONVST RD
INTERNAL
CLOCK
SLEEPHBEN
NAP
ZEROING SWITCHES
V
SS
(0V FOR UNIPOLAR MODE OR
–5V FOR BIPOLAR MODE)
V
DD
A
IN
–
A
IN
+
V
REF
REFRDY
AGND
DGND
12
LTC1277 • BD
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT LATCHES
2.42V REF
TEST CIRCUITS
Load Circuits for Output Float DelayLoad Circuits for Access Timing
3k C
L
DBN
DGND
A) HIGH-Z TO V
OH
(t
9
)
AND V
OL
TO V
OH
(t
6
)
C
L
DBN
3k
5V
B) HIGH-Z TO V
OL
(t
9
)
AND V
OH
TO V
OL
(t
6
)
DGND
1274/77 • TC01
3k
10pF
DBN
DGND
A) V
OH
TO HIGH-Z
10pF
DBN
3k
5V
B) V
OL
TO HIGH-Z
DGND
1274/77 • TC02