Datasheet
14
LTC1274/LTC1277
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
Figure 8. For bipolar mode, a 0.1µF ceramic provides
adequate bypassing for the V
SS
pin. The capacitors must
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
Input signal leads to A
IN
and signal return leads from
AGND (Pin 3 for LTC1274, Pin 4 for LTC1277) should be
kept as short as possible to minimize input noise cou-
pling. In applications where this is not possible a shielded
cable between source and ADC is recommended.
Also, since any potential difference in grounds between
the signal source and the ADC appears as an error voltage
in series with the input signal, attention should be paid to
reducing the ground circuit impedances as much as
possible.
A single point analog ground separate from the logic
system ground should be established with an analog
ground plane at AGND or as close as possible to the ADC.
DGND (Pin 12) and all other analog grounds should be
connected to this single analog ground point. No other
digital grounds should be connected to this analog ground
point. Low impedance analog and digital power supply
common returns are essential to low noise operation of
the ADC and the foil width for these tracks should be as
wide as possible. In applications where the ADC data
outputs and control signals are connected to a continu-
ously active microprocessor bus, it is possible to get
errors in conversion results. These errors are due to
feedthrough from the microprocessor to the successive
approximation comparator. The problem can be elimi-
nated by forcing the microprocessor into a Wait state
during conversion or by using three-state buffers to
isolate the ADC data bus. Figure 9 is a typical application
circuit for the LTC1274.
Figure 8. Power Supply Grounding Practice
Figure 9. LTC1274 Typical Circuit
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A
IN
V
REF
AGND
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
DGND
V
DD
V
SS
BUSY
CS
RD
CONVST
SLEEP
REFRDY
D0
D1
D2
D3
LTC1274
0.1µF
+
10µF
ANALOG INPUT
(0V TO 4.095V)
2.42V
V
REF
OUTPUT
10µF
0.1µF
5V
12-BIT
PARALLEL
BUS
µP
CONTROL
LINES
CONVERSION START INPUT
SLEEP MODE INPUT
REFERENCE READY SIGNAL
LTC1274/77 • F09
+
LTC1274/77 • F08
A
IN
AGND V
REF
AV
DD
DV
DD
DGND
LTC1274
DIGITAL
SYSTEM
0.1µF
+
–
ANALOG GROUND PLANE
GROUND CONNECTION
TO DIGITAL CIRCUITRY
ANALOG
INPUT
CIRCUITRY
3 2 24 17 12
1
0.1µF
10µF10µF