Datasheet

10
LTC1274/LTC1277
TI I G DIAGRA S
W
W
U
CS to RD Setup Timing
CS to CONVST Setup Timing
t
1
CS
RD
LTC1274/77 • TD01
t
2
CS
CONVST
LTC1274/77 • TD02
NAP to CONVST Wake-Up Timing (LTC1277)
SLEEP to REFRDY Wake-Up Timing
t
3
NAP
CONVST
LTC1274/77 • TD03
t
14
SLEEP
REFRDY
LTC1274/77 • TD04
APPLICATIONS INFORMATION
WUU
U
CONVERSION DETAILS
The LTC1274/LTC1277 use a successive approximation
algorithm and an internal sample-and-hold circuit to con-
vert an analog signal to a 12-bit parallel output. The ADCs
are complete with a precision reference and an internal
clock. The control logic provides easy interface to micro-
processors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of conversion the successive approxi-
mation register (SAR) is reset. Once a conversion cycle
has begun it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC out-
put is sequenced by the SAR from the most significant bit
(MSB) to the least significant bit (LSB). Referring to
Figure 1, the A
IN
(LTC1274) or A
IN
+
(LTC1277) input con-
nects to the sample-and-hold capacitor during the acquire
phase, and the comparator offset is nulled by the feedback
switch. In this acquire phase, a minimum delay of 2µs will
provide enough time for the sample-and-hold capacitor to
acquire the analog signal. During the convert phase, the
comparator feedback switch opens, putting the comparator
into the compare mode. The input switch connects C
SAMPLE
to ground (LTC1274) or A
IN
–
(LTC1277), injecting the
analog input charge onto the summing junction. This input
charge is successively compared with the binary-weighted
charges supplied by the capacitive DAC. Bit decisions are
made by the high speed comparator. At the end of a
conversion, the DAC output balances the A
IN
(LTC1274) or
A
IN
+
– A
IN
–
(LTC1277) input charge. The SAR contents (a 12-
bit data word) which represent the A
IN
(LTC1274) or
A
IN
+
– A
IN
–
(LTC1277) are loaded into the 12-bit output latches.
V
DAC
1274 • F01
+
–
C
DAC
DAC
SAMPLE
HOLD
C
SAMPLE
S
A
R
12-BIT
LATCH
COMPAR-
ATOR
SAMPLE
SI
A
IN
Figure 1. LTC1274 A
IN
Input
DYNAMIC PERFORMANCE
The LTC1274/LTC1277 have excellent high speed sam-
pling capability. FFT (Fast Fourier Transform) test tech-
niques are used to test the ADCs’ frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital output