Datasheet

LTC1272
16
1272fc
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APPLICATIONS INFORMATION
Figure 17. ROM Mode, Two Byte Read Timing Diagram
Table 5. ROM Mode, Two Byte Read Data Bus Status
Data Outputs D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8
First Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Second Read Low Low Low Low DB11 DB10 DB9 DB8
Third Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
OLD DATA
DB7-DB0
NEW DATA
DB11-DB8
TRACK
HOLD
DATA
BUSY
RD
CS
RD
LTC1272 • F17
t
8
t
1
t
2
t
3
t
CONV
t
11
t
9
t
8
t
9
t
5
t
1
t
4
t
5
t
10
t
3
t
7
t
3
t
7
t
12
t
12
HBEN
t
7
t
4
t
1
t
8
t
9
NEW DATA
DB7-DB0
t
2
t
4
t
5
ROM Mode, Two Byte READ
As previously mentioned for a two byte read, only data
outputs D7 . . . D0/8 are used. Conversion is started in
the normal way with a Read operation and the data output
status is the same as the ROM Mode, Parallel Read. See
Figure 17 timing diagram and Table 5 data bus status.
Two more Read operations are required to access the new
conversion result. A delay equal to the LTC1272 conversion
time must be allowed between conversion start and the
second data Read operation. The second Read operation,
with HBEN high, disables conversion start and places the
high byte (4 MSBs) on data outputs D3/11 . . . DO18. A
third read operation accesses the low data byte (DB7
. . . DB0) and starts another conversion. The 4 MSB’s
appear on data outputs D11 . . . D8 during all three read
operations above.
Microprocessor Interfacing
The LTC1272 is designed to interface with microproces-
sors as a memory mapped device. The CS and RD control
inputs are common to all peripheral memory interfacing.
The HBEN input serves as a data byte select for 8-bit pro-
cessors and is normally connected to the microprocessor
address bus.
MC68000 Microprocessor
Figure 18 shows a typical interface for the MC68000. The
LTC1272 is operating in the Slow Memory Mode. Assuming
the LTC1272 is located at address C000, then the following
single 16-bit Move instruction both starts a conversion
and reads the conversion result:
Move.W $C000,D0