Datasheet

LTC1272
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1272fc
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APPLICATIONS INFORMATION
as in Figure 5. Nevertheless, even without observing this
guideline, the LTC1272 is still compatible with AD7572
synchronization modes, with no increase in linearity error.
This means that either the falling or rising edge of CLK IN
may be near RD’s falling edge.
Driving the Analog Input
The analog input of the LTC1272 is much easier to drive
than that of the AD7572. The input current is not modulated
by the DAC as in the AD7572. It has only one small current
spike from charging the sample-and-hold capacitor at the
end of the conversion. During the conversion the analog
input draws only DC current. The only requirement is that
the amplifier driving the analog input must settle after the
small current spike before the next conversion is started.
Any op amp that settles in 1µs to small current transients
will allow maximum speed operation. If slower op amps
are used, more settling time can be provided by increasing
the time between conversions. Suitable devices capable
of driving the LTC1272 A
IN
input include the LT1006 and
LT1007 op amps.
Internal Clock Oscillator
Figure 6 shows the LTC1272 internal clock circuit. A crystal
or ceramic resonator may be connected between CLK IN
(Pin 17) and CLK OUT (Pin 18) to provide a clock oscillator
for ADC timing. Alternatively the crystal/resonator may be
omitted and an external clock source may be connected
to CLK IN. For an external clock the duty cycle is not
critical. An inverted CLK IN signal will appear at the CLK
OUT pin as shown in the operating waveforms of Figure 7.
Capacitance on the CLK OUT pin should be minimized for
best analog performance.
Internal Reference
The LTC1272 has an on-chip, temperature compensated,
curvature corrected, bandgap reference, which is factory
trimmed to 2.42V ±1%. It is internally connected to the
DAC and is also available at pin 2 to provide up to 1mA
current to an external load.
For minimum code transition noise the reference output
should be decoupled with a capacitor to filter wideband
noise from the reference (10µF tantalum in parallel with
a 0.1µF ceramic). A simplified schematic of the reference
with its recommended decoupling is shown in Figure 8.
Figure 6. LTC1272 Internal Clock Circuit
Figure 5. RD and CLK IN for Synchronous Operation
LTC1272 • F05
CS & RD
BUSY
CLK IN
≥ 40ns*
t
2
t
14
t
CONV
t
13
DB0
(LSB)
DB1DB10DB11
(MSB)
UNCERTAIN CONVERSION TIME FOR 30ns < t
14
< 180ns
THE LTC1272 IS ALSO COMPATIBLE WITH THE AD7572 SYNCHRONIZATION MODES.
*
LTC1272 • F06
CLK OUT
CLK IN
C1
C2
1M
CLOCK
LTC1272
NOTES:
LTC1272-3 – 4MHz CRYSTAL/CERAMIC RESONATOR
LTC1272-8 – 1.6MHz CRYSTAL/CERAMIC RESONATOR
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