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LTC1266

LTC1266-3.3/LTC1266-5

Synchronous Regulator

Controller for

N- or P-Channel MOSFETs

■

Ultrahigh Efficiency: Over 95% Possible

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Drives N-Channel MOSFET for High Current or

P-Channel MOSFET for Low Dropout

■

Pin Selectable Burst Mode Operation

■

1% Output Accuracy (LTC1266A)

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Pin Selectable Phase of Topside Driver for Boost

or Step-Down Operation

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Wide V

Range: 3.5V to 20V

■

On-Chip Low-Battery Detector

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High Efficiency Maintained Over Large Current Range

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Low 170µA Standby Current at Light Loads

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Current Mode Operation for Excellent Line and Load

Transient Response

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Logic Controlled Micropower Shutdown: I

< 40µA

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Short-Circuit Protection

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Synchronous Switching with Nonoverlaping Gate Drives

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Available in 16-Pin Narrow SO Package

The LTC

1266 series is a family of synchronous switching

regulator controllers featuring automatic Burst Mode

operation to maintain high efficiencies at low output

currents. These devices drive external power MOSFETs at

switching frequencies up to 400kHz using a constant off-

time current mode architecture providing constant ripple

current in the inductor. They can drive either an N-channel

or a P-channel topside MOSFET.

The operating current level is user-programmable via an

external current sense resistor. Wide input supply range

allows operation from 3.5V to 18V (20V maximum).

Constant off-time architecture provides low dropout regu-

lation limited only by the R

DS(ON)

of the topside MOSFET

(when using the P-channel) and the resistance of the

inductor and current sense resistor.

The LTC1266 series combines synchronous switching for

maximum efficiency at high currents with an automatic

low current operating mode, called Burst Mode

operation,

which reduces switching losses. Standby power is re-

duced to only 1mW at V

= 5V (at I

OUT

= 0). Load currents

in Burst Mode

operation are typically 0mA to 500mA.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode is a trademark of Linear Technology Corporation.

Figure 1. High Efficiency Step-Down Converter

LTC1266-3.3 Efficiency

LOAD CURRENT (A)

0.01

EFFICIENCY (%)

100

0.1 51

1266 TA02

= 5V

0V = NORMAL

>1.5V = SHUTDOWN

N-CHANNEL

Si9410

100µF

×2

5µH

MBR0530T1

SENSE

0.02Ω

100k

OUT

3.3V

LOW BAT OUT

4V TO 9V

SGND

180pF

3300pF

470Ω

OUT

330µF

× 2

MBRS130LT3

1266 TA01

BDRIVEBINH

PGND

N-CHANNEL

Si9410

PWR V

OUT

PINV

LTC1266-3.3

SHDN

SENSE

TDRIVE

SENSE

–

1000pF

0.1µF

*TOKO 919AS-4R7M

LOW BAT IN

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Notebook and Palmtop Computers

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Portable Instruments

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Cellular Telephones

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DC Power Distribution Systems

■

GPS Systems

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

Summary of content (20 pages)

PAGE 1
LTC1266 LTC1266-3.3/LTC1266-5 Synchronous Regulator Controller for N- or P-Channel MOSFETs U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Ultrahigh Efficiency: Over 95% Possible Drives N-Channel MOSFET for High Current or P-Channel MOSFET for Low Dropout Pin Selectable Burst Mode Operation 1% Output Accuracy (LTC1266A) Pin Selectable Phase of Topside Driver for Boost or Step-Down Operation Wide VIN Range: 3.
PAGE 2
LTC1266 LTC1266-3.3/LTC1266-5 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) Input Supply Voltage (Pins 2, 5) ............... 20V to – 0.3V Continuous Output Current (Pins 1, 16) .............. 50mA Sense Voltages (Pins 8, 9) ....................... 13V to – 0.3V SHDN Voltage (Pin 11) ............................. 12V to – 0.3V PINV, BINH, LBIN (Pins 3, 4, 13)................20V to – 0.3V LBOUT Output Current ...........................................
PAGE 3
LTC1266 LTC1266-3.3/LTC1266-5 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 10V, VSHDN = VBINH = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VSENSE 1 Current Sense Threshold (Burst Mode Operation Enabled) LTC1266 VBINH = 0V LTC1266-3.3 LTC1266-5 VSENSE 2 Current Sense Threshold (Burst Mode Operation Disabled) LTC1266 LTC1266-3.3 LTC1266-5 VSENSE – = 3.3V, VFB = VOUT/2.
PAGE 4
LTC1266 LTC1266-3.3/LTC1266-5 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS IQ1 VIN Pin DC Supply Current (Note 3) Normal Mode Sleep Mode Shutdown PWR VIN DC Supply Current (Note 3) Normal Mode Sleep Mode Shutdown IQ2 VSENSE1 VSENSE2 Current Sense Threshold (Burst Mode Operation Enabled) LTC1266CS, LTC1266IS LTC1266CS LTC1266IS LTC1266-3.3, LTC1266-5 (I and C) LTC1266CS-3.3, LTC1266CS-5 LTC1266IS-3.
PAGE 5
LTC1266 LTC1266-3.3/LTC1266-5 U W TYPICAL PERFOR A CE CHARACTERISTICS Line Regulation Efficiency vs Input Voltage 100 FIGURE 1 CIRCUIT ILOAD = 2.5A ILOAD = 5A 85 ILOAD = 100mA 80 10 0 –10 75 8 5 6 7 INPUT VOLTAGE (V) 4 – 40 9 4 5 6 7 INPUT VOLTAGE (V) ILOAD = 1A 0 –10 16 0 20 4 8 12 VIN = 5V (Burst Mode OPERATION INHIBITED) 0 2.0 1.5 1.0 LOAD CURRENT (A) 0.5 1.5 1.0 Supply Current in Shutdown 25 50 20 40 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 2.
PAGE 6
LTC1266 LTC1266-3.3/LTC1266-5 U W TYPICAL PERFOR A CE CHARACTERISTICS Operating Frequency vs (VIN – VOUT) Voltage 100 3.0 VSENSE– = VOUT NORMALIZED FREQUENCY OFF-TIME (µs) VOUT = 3.3V 2.5 80 60 40 20 Current Sense Threshold Voltage 200 MAX THRESHOLD 0°C 150 SENSE VOLTAGE (mV) Off-Time vs Output Voltage 70°C 2.0 25°C 1.5 1.0 MIN THRESHOLD (Burst Mode OPERATION ENABLED) 50 MIN THRESHOLD (Burst Mode OPERATION INHIBIT) 0 0.5 LTC1266-5 100 LTC1266-3.
PAGE 7
LTC1266 LTC1266-3.3/LTC1266-5 W FU CTIO AL DIAGRA Pin 10 Connection Shown for LTC1266-3.3 and LTC1266-5; Changes Create LTC1266 – U U LBIN 13 + 1.25V REFERENCE VIN PWR VIN 14 LBOUT LB 2 3 PINV 1 TDRIVE SIGNAL GROUND 12 SENSE+ SENSE – 9 8 ADJUSTABLE VERSION VFB 16 BDRIVE BINH 10 4 – 15 PGND V + SLEEP – C R + Q + S S VTH1 13k + 6 CT 5pF VOS – ITH 7 T OFF-TIME CONTROL VIN SENSE – VFB G MAX ON-TIME CONTROL ENABLE 100k + VTH2 + VTRIP – – – PINV SHDN 11 1.
PAGE 8
LTC1266 LTC1266-3.3/LTC1266-5 U OPERATIO When the voltage on the timing capacitor has discharged past VTH1, comparator T trips, setting the flip-flop. This causes the bottom-side output to switch off and the topside output to switch on (ground for P-channel and Power VIN for N-channel). The cycle then repeats. As the load current increases, the output voltage decreases slightly. This causes the output of the gain stage (Pin 7) to increase the current comparator threshold, thus tracking the load current.
PAGE 9
LTC1266 LTC1266-3.3/LTC1266-5 U W U U APPLICATIO S I FOR ATIO RSENSE Selection for Output Current RSENSE is chosen based on the required output current. The LTC1266 series current comparator has a threshold range which extends from a minimum of 25mV/RSENSE (when Burst Mode operation is enabled) to a maximum of 155mV/RSENSE.
PAGE 10
LTC1266 LTC1266-3.3/LTC1266-5 U W U U APPLICATIO S I FOR ATIO As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The complete expression for operating frequency of the circuit in Figure 1 is given by: f= 1 tOFF ) 1– VOUT VIN ) where: tOFF = 1.3 • 104 • CT • ) ) VREG VOUT VREG is the desired output voltage (i.e., 5V, 3.3V). VOUT is the measured output voltage. Thus VREG/VOUT = 1 in regulation.
PAGE 11
LTC1266 LTC1266-3.3/LTC1266-5 U W U U APPLICATIO S I FOR ATIO From the duty cycles, the required RDS(ON) for each MOSFET can be derived: TS RDS(ON) = VIN • PT VOUT • IMAX2 • (1 + δT) BS RDS(ON) = VIN • PB (VIN – VOUT) • IMAX2 • (1 + δB) where PT and PB are the allowable power dissipations and δT and δB are the temperature dependencies of RDS(ON). PT and PB will be determined by efficiency and/or thermal requirements (see Efficiency Considerations).
PAGE 12
LTC1266 LTC1266-3.3/LTC1266-5 U W U U APPLICATIO S I FOR ATIO Driving N-Channel Topside MOSFETs 1000 L = 50µH RSENSE = 0.02Ω COUT (µF) 800 L = 25µH RSENSE = 0.02Ω 600 400 200 0 L = 50µH RSENSE = 0.05Ω 0 1 3 4 2 (VIN – VOUT) VOLTAGE (V) 5 1266 F04 Figure 4. Minimum Value of COUT series would normally be in continuous operation. The output remains in regulation at all times. This minimum capacitance requirement may be relaxed if Burst Mode operation is disabled.
PAGE 13
LTC1266 LTC1266-3.3/LTC1266-5 U U W U APPLICATIO S I FOR ATIO 100 VOUT = 3.3V Burst Mode OPERATION ENABLED TOPSIDE N-CHANNEL WITH CHARGE PUMP 500 90 TOPSIDE P-CHANNEL 400 EFFICIENCY (%) VIN–V0UT (mV) AT DROPOUT 600 300 200 0 0 1 3 2 LOAD CURRENT Burst Mode OPERATION INHIBITED 70 TOPSIDE N-CHANNEL WITH POWER VIN = 12V 100 80 4 60 0.01 5 0.1 1 LOAD CURRENT (A) 1266 F07 1266 F05 Figure 5. Comparison of Dropout Performance VIN R2 LTC1266 – R1 5 LBOUT + 1.
PAGE 14
LTC1266 LTC1266-3.3/LTC1266-5 U W U U APPLICATIO S I FOR ATIO Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc.
PAGE 15
LTC1266 LTC1266-3.3/LTC1266-5 U W U U APPLICATIO S I FOR ATIO operation, the DC supply current represents the lone (and unavoidable) loss component which continues to become a higher percentage as output current is reduced. As expected the I2R losses dominate at high load currents. Other losses including CIN and COUT ESR dissipative losses, MOSFET switching losses, Schottky conduction losses during deadtime and inductor core losses, generally account for less than 2% total additional loss.
PAGE 16
LTC1266 LTC1266-3.3/LTC1266-5 U W U U APPLICATIO S I FOR ATIO Troubleshooting Hints Since efficiency is critical to LTC1266 series applications, it is very important to verify that the circuit is functioning correctly in both continuous and Burst Mode operation. The waveform to monitor is the voltage on the timing capacitor, Pin 6. In continuous mode (ILOAD > IBURST) the voltage on the CT pin should be a sawtooth with a 0.9VP-P swing. This voltage should never dip below 2V as shown in Figure 9a.
PAGE 17
LTC1266 LTC1266-3.3/LTC1266-5 U W U U APPLICATIO S I FOR ATIO 3. Are the SENSE– and SENSE+ leads routed together with minimum PC trace spacing? The 1000pF capacitor between Pins 8 and 9 should be as close as possible to the LTC1266. helpful in eliminating instabilities at high input voltage and high output loads. 6. Is the shutdown (Pin 11) actively pulled to ground during normal operation? The shutdown pin is high impedance and must not be allowed to float.
PAGE 18
LTC1266 LTC1266-3.3/LTC1266-5 U TYPICAL APPLICATIO S (Layout Assist Schematics) VIN 4.3V TO 10V (VIN (MIN) = 3.5V IF ILOAD < 100mA 0.068Ω + 0.
PAGE 19
LTC1266 LTC1266-3.3/LTC1266-5 U TYPICAL APPLICATIO S (Layout Assist Schematics) VIN 4V TO 9V 0.1µF MBR0530T1 1 2 3 4 BINH 5 6 7 CT 220pF CC 3300pF 8 TDRIVE BDRIVE PWR VIN PGND PINV LBOUT BINH LBIN LTC1266-3.3 VIN SGND CT SHDN ITH NC SENSE – RC 470Ω SENSE + 16 Si4410DY + Si4410DY D1 MBRS340T3 47µF 10V OS-CON 3× 15 14 13 12 11 SHUTDOWN L* 5µH 10 COUT 330µF 10V 3× + 9 1000pF RSENSE 0.01Ω 1266 F14 *MAGNETICS Kool Mµ 77120-A7 VOUT 3.3V 10A Figure 14. All N-Channel 5V to 3.
PAGE 20
LTC1266 LTC1266-3.3/LTC1266-5 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 – 0.394* (9.804 – 10.008) 16 15 14 13 12 11 10 9 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 2 3 5 4 0.053 – 0.069 (1.346 – 1.752) 0.014 – 0.019 (0.355 – 0.483) TYP 7 8 0.004 – 0.010 (0.101 – 0.