Datasheet

4
LTC1262
BLOCK DIAGRAM
W
TI I G DIAGRA S
WWU
Figure 2. LTC1262 Timing Circuit
–
+
S3B
S3D
S3A
S4A
S4B
S1 AND S2 SHOWN WITH SHDN PIN LOW.
S3A, S3B, S3C, S3D, S4A AND S4B SHOWN WITH OSCILLATOR OUTPUT LOW AND V
DIV
< V
BGAP
– V
HYST
.
COMPARATOR HYSTERISIS IS ±V
HYST
.
C1
C1
+
C1
–
C2
C2
+
C2
–
CHARGE
PUMP
S3C
D2
D1
V
BGAP
S1
LTC1262 • BD
S2
R3
R1
R2
V
OUT
V
CC
SHDN
GND
C
OUT
BANDGAP
REFERENCE
OSCILLATOR
C
IN
V
DIV
+
+
Figure 1. LTC1262 Timing Diagram
1
2
3
4
8
7
6
5

C1
0.22µF
C2
0.22µF
C
OUT

4.7µF
V
SHUTDOWN
V
OUT
LTC1262 • F02
V
CC

4.75V TO 5V
C
IN

4.7µF
C1
–

C1
+

C2
–

C2
+
SHDN
GND
V
OUT

V
CC
LTC1262
+
+
1.4V
5.1V
1.4V
V
SHDN
V
OUT
V
CC
V
CC
V
OUT
11.4V
0V
LTC1262 • F01
t
OFF
t
ON