Datasheet

LTC1235
7
1235fa
PIN FUNCTIONS
high when ever there is a transition on the WDI pin, or
LOW LINE goes low. The watchdog timer can be disabled
by fl oating WDI (see Figure 11).
RESET
(Pin 15): Logic output for μP reset control. The
LTC1235 provides three ways to generate μP reset. First,
whenever V
CC
falls below either the reset voltage threshold
(4.65V, typically) or V
BATT
, RESET goes active low. After
V
CC
returns to 5V, the reset pulse generator forces RESET
to remain active low for a minimum of 140ms. Second,
when the watchdog timer is enabled but not serviced
prior to the time-out period, the reset pulse generator
also forces RESET to active low for a minimum of 140ms
for every time-out period (see Figure 11). Third, when the
PB RST pin stays active low for a minimum of 40ms,
RESET is forced low by reset pulse generator. The RESET
signal will remain active low for a minimum of 140ms from
the moment the push-button reset input is released from
logic low level.
RESET
(Pin 16): RESET is an active high logic output. It
is the inverse of RESET.
BLOCK DIAGRAM
CHARGE
PUMP
M2
M1
V
BATT
V
CC
PFI
60k
V
CC
WDI
RESET
BATT ON
V
OUT
1.3V
GND
C1
–
+
–
+
C2
TRANSITION
DETECTOR
–
+
WDO
RESET
PFO
LOW LINE
CE OUT
1235 BD
CE IN
MEMORY
LOGIC
RESET PULSE
GENERATOR
WATCHDOG
TIMER
LEVEL SENSE
AND
DEBOUNCE
OSC
BACKUP
PB RST