Datasheet
13
LTC1197/LTC1197L
LTC1199/LTC1199L
1197/99 F02
CLK
CS
t
dDO
t
suCS
B0*
B1B2B3B4
B5
B6B7
B8B9
NULL
BITS
Hi-Z
1413121110987654321 15 16
1
D
OUT
D
IN
HI-Z
START
DUMMY
DON’T CARE
ODD/
SIGN
SGL/
DIFF
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT ZEROS INDEFINITELY
t
en
t
CYC
(16 CLKs)*
t
CONV
(10.5 CLKs)
POWER
DOWN
t
SMPL
(1.5 CLKs)
Figure 2. LTC1199/LTC1199L Operating Sequence
transfer and all leading zeros that precede this logical one
will be ignored. After the start bit is received the remaining
bits of the input word will be clocked in. Further inputs on
the D
IN
pin are then ignored until the next CS cycle.
Multiplexer (MUX) Address
The bits of the input word following the start bit assign the
MUX configuration for the requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+” and
“–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured with
respect to GND. Only the + inputs have sample-and-holds.
Signals applied at the – inputs must not change more than
the required accuracy during the conversion.
Multiplexer Channel Selection
MUX ADDRESS
SGL/DIFF
1
1
0
0
ODD/SIGN
0
1
0
1
CHANNEL #
0
+
+
–
1
+
–
+
GND
–
–
1197/99 AI02
The LTC1197/LTC1197L do not require a configuration
input word and have no D
IN
pin. A falling CS initiates data
transfer as shown in the LTC1197/LTC1197L operating
sequence. After CS falls, the second CLK pulse enables
D
OUT
. After two null bits, the A/D conversion result is output
on the D
OUT
line in MSB-first format. Bringing CS high
resets the LTC1197/LTC1197L for the next data exchange
and minimizes the supply current if CLK is continuously
running.
INPUT DATA WORD (LTC1199/LTC1199L ONLY)
The LTC1199 4-bit data word is clocked into the D
IN
input
on the rising edge of the clock after CS goes low and the
start bit has been recognized. Further inputs on the D
IN
pin
are then ignored until the next CS cycle. The input word is
defined as follows:
SGL/
DIFF
ODD/
SIGN
DUMMYSTART
MUX
ADDRESS
1197/99 AI01
Start Bit
The first “logical one” clocked into the D
IN
input after CS
goes low is the start bit. The start bit initiates the data
APPLICATIO S I FOR ATIO
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