Datasheet

15
LTC1159
LTC1159-3.3/LTC1159-5
1) Are the signal and power grounds segregated? The
LTC1159 signal ground must connect separately to the
(–) plate of C
OUT
. The other ground pin(s) should return to
the source of the N-channel MOSFET, anode of the Schot-
tky diode and (–) plate of C
IN
, which should have as short
lead lengths as possible.
2) Does the LTC1159 SENSE
–
pin connect to a point close
to R
SENSE
and the (+) plate of C
OUT
? In adjustable applica-
tions, the resistive divider R1, R2 must be connected
between the (+) plate of C
OUT
and signal ground.
3 ) Are the SENSE
–
and SENSE
+
leads routed together
with minimum PC trace spacing? The differential
decoupling capacitor between the two SENSE pins should
be as close as possible to the LTC1159. Up to 100Ω may
be placed in series with each sense lead to help decouple
the SENSE pins. However, when these resistors are used,
the capacitor should be no larger than 1000pF.
4) Does the (+) plate of C
IN
connect to the source of the
P-channel MOSFET as closely as possible? An additional
0.1µF ceramic capacitor between V
IN
and power ground
may be required in some applications.
5) Is the V
CC
decoupling capacitor connected closely be-
tween the V
CC
pins of the LTC1159 and power ground?
This capacitor carries the MOSFET driver peak currents.
6) In adjustable versions, the feedback pin is very sensitive
to pickup from the switch node. Care must be taken to
isolate V
FB
from possible capacitive coupling of the induc-
tor switch signal.
7) Is the SHDN1 pin actively pulled to ground during
normal operation? SHDN1 is a high impedance pin and
must not be allowed to float.
Troubleshooting Hints
Since efficiency is critical to LTC1159 applications it is very
important to verify that the circuit is functioning correctly
in both continuous and Burst Mode operation. The wave-
form to monitor is the voltage on the C
T
pin .
In continuous mode (I
LOAD
> I
BURST
) the voltage should be
a sawtooth with a 0.9V
P-P
swing. This voltage should never
dip below 2V as shown in Figure 9a. When the load current
is low (I
LOAD
< I
BURST
), Burst Mode operation should occur
with the C
T
waveform periodically falling to ground as
shown in Figure 9b.
If the C
T
pin is observed falling to ground at high output
currents, it indicates poor decoupling or improper ground-
ing. Refer to the Board Layout Checklist.
3.3V
0V
(a) CONTINUOUS MODE OPERATION
3.3V
0V
(b) Burst Mode OPERATION
LTC1159 • F09
Figure 9. C
T
Pin 6 Waveforms
APPLICATIO S I FOR ATIO
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