Datasheet

5
LTC1155
PIN FUNCTIONS
UUU
The supply pin of the LTC1155 should not be forced below
ground as this may result in permanent damage to the
device. A 300Ω resistor should be inserted in series with
the ground pin if negative supply voltages are anticipated.
Drain Sense Pin
As noted previously, the drain sense pin is compared
against the supply pin voltage. If the voltage at this pin is
more than 100mV below the supply pin, the input latch will
be reset and the MOSFET gate will be quickly discharged.
Cycle the input to reset the short-circuit latch and turn the
MOSFET back on.
This pin is also a high impedance CMOS gate with ESD
protection and, therefore, should not be forced beyond the
power supply rails. To defeat the over current protection,
short the drain sense to supply.
Some loads, such as large supply capacitors, lamps or
motors require high inrush currents. An RC time delay
must be added between the sense resistor and the drain
sense pin to ensure that the drain sense circuitry does not
false trigger during start-up. This time constant can be set
from a few microseconds to many seconds. However, very
long delays may put the MOSFET in risk of being destroyed
by a short-circuit condition (see Applications Information
section).
OPERATIO
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The LTC1155 contains two independent power MOSFET
gate drivers and protection circuits (refer to the Block
Diagram for details). Each half of the LTC1155 consists of
the following functional blocks:
TTL and CMOS Compatible Inputs
Each driver input has been designed to accommodate a
wide range of logic families. The input threshold is set at
1.3V with approximately 100mV of hysteresis.
A voltage regulator with low standby current provides
continuous bias for the TTL to CMOS converters. The TTL
to CMOS converter output enables the rest of the circuitry.
In this way the power consumption is kept to a minimum
in the standby mode.
Internal Voltage Regulation
The output of the TTL to CMOS converter drives two
regulated supplies which power the low voltage CMOS
logic and analog blocks. The regulator outputs are isolated
from each other so that the noise generated by the charge
pump logic is not coupled into the 100mV reference or the
analog comparator.
W
IDAGRA
B
L
O
C
K
1155 BD
GATE
ONE
SHOT
FAST/SLOW
GATE CHARGE
LOGIC
OSCILLATOR
AND CHARGE
PUMP
INPUT
LATCH
GATE CHARGE
AND DISCHARGE
CONTROL LOGIC
R
S
10µs
DELAY
COMP
100mV
REFERENCE
DRAIN
SENSE
ANALOG SECTION
ANALOG DIGITAL
TTL-TO-CMOS
CONVERTER
V
S
IN
LOW STANDBY
CURRENT
REGULATOR
GND
VOLTAGE
REGULATORS